A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
2
1
3
4
5
6
7
8
2
1
3
4
5
6
7
8
C2490
220
6.3V
MZA
OF PRINTING AND SUBJECT TO CHANGE WITHOUT NOTICE
NOTE: THIS SCHEMATIC DIAGRAM IS THE LATEST AT THE TIME
WAS RECEIVED IN GOOD CONDITION AND PICTURE IS NORMAL.
WITH THE DIGITAL TESTER WHEN THE COLOR BROADCAST
NOTE:THE DC VOLTAGE AT EACH PART WAS MEASURED
JG2411
B2406
FCM1608KF-151T06
B2405
FCM1608KF-151T06
R2421
1K
+-1%
R2420
1K
+-1%
R2412
15 +-1%
R2415
15 +-1%
R2416
15 +-1%
R2417
10K
R2418
1K+-1%
R2419
1K+-1%
R2413
1K
+-1%
R2414
1K
+-1%
C2461
0.1
B
C2479
0.1 B
C2480
0.1
B
C2456
10
C
C2460
0.1
B
C2462
0.1 B
C2475
0.1 B
C2471
0.1 B
C2467
0.1 B
C2472
1 B
C2470
1 B
C2473
0.1 B
C2474
1 B
C2469
0.1 B
C2468
1 B
C2466
1 B
C2465
0.1 B
C2464
1 B
C2463
0.1 B
C2476
1 B
C2478
10 C
C2477
0.1 B
C2482
0.1 B
C2484
0.1 B
C2486
0.1 B
C2487
0.1 B
C2485
0.1 B
C2483
0.1 B
C2494
1 B
C2496
1 B
C2497
1 B
C2498
1 B
C2499
1 B
C2493
0.1 B
C2495
0.1 B
C2481
0.1 B
C2492
1 B
C2458
0.1 B
C2459
0.1 B
C2457
0.1 B
C2488
0.1
B
C2489
1B
E24
AC24
G26
D20
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
J1
J7
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
M2
D7
R2
D1
D9
L3
B1
IC2402
HYB18T512161BF-25
512Mbit DDR2 SDRAM IC
L2
B9
P7
D3
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
J2
R3
R7
R8
A2
E2
L1
K2
K8
J8
B3
F3
K9
F7
E8
B7
A8
K3
L8
L7
K7
D21
D22
F23
G23
G24
H23
K23
U23
V23
W23
Y23
AC19
AC20
AC21
AC22
M23
J23
AC23
L23
D24
R23
T23
AD25
AB23
AC25
G25
AD26
H25
H26
AA26
AA25
H24
W25
J26
U25
K26
U24
K25
Y24
K24
V25
L26
V26
L25
T26
M26
Y25
M25
W24
M24
Y26
N24
T24
P26
T25
P25
W26
P24
V24
U26
AA24
AC26
L24
AB25
N25
AB24
J24
R26
N26
AB26
J25
R25
IC2401
X242
ATSC/CLEAR CABLE ASIC IC
R24
MEM_DQA0
MEM_AA0
MEM_AA15
MEM_DQA14
MEM_DQA1
MEM_AA1
MEM_AA14
MEM_DQA12
MEM_DQA2
MEM_AA2
MEM_DQA15
MEM_DQA3
MEM_AA3
MEM_AA12
MEM_DQA9
MEM_DQA4
MEM_AA4
MEM_AA11
MEM_DQA8
MEM_DQA5
MEM_AA5
MEM_AA10
MEM_DQA13
MEM_DQA6
MEM_AA6
MEM_AA5
MEM_DQA11
MEM_DQA7
MEM_AA7
MEM_AA7
MEM_DQA10
MEM_DQA8
MEM_AA8
MEM_AA2
MEM_DQA6
MEM_DQA9
MEM_AA9
MEM_AA6
MEM_DQA7
MEM_DQA10
MEM_AA10
MEM_AA8
MEM_DQA2
MEM_DQA11
MEM_AA11
MEM_AA4
MEM_DQA3
MEM_DQA12
MEM_AA12
MEM_AA3
MEM_DQA4
MEM_DQA13
MEM_AA13
MEM_AA9
MEM_DQA0
MEM_DQA14
MEM_AA14
MEM_AA1
MEM_DQA5
MEM_DQA15
MEM_AA15
MEM_AA0
MEM_DQA1
MRAS#
MCLK#
MEM_DQM0#
MCAS#
MCLK
MEM_DQM1#
MRWE#
MCS#
MCKEN
MEM_QS0
MEM_ODT
MEM_QS0#
MCKEN
MEM_QS1
MCLK
MCS#
MEM_QS1#
MCLK#
MRWE#
MRAS#
MCAS#
MEM_DQM0#
MEM_DQM1#
MEM_ODT
MEM_QS0
MEM_QS0#
MEM_QS1
MEM_QS1#
+3.3V
VDDC_1.0V
GND
+2.5V_IO
MEM[1.8V]
H-4
H-3
PCBDH0
CEF276
SDRAM SCHEMATIC DIAGRAM
PESD_1
MPVDD
MVREFS
VDDR1_0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VSS1
VSS2
VSS3
VSS4
VSS5
VSSQ10
VSSQ9
VSSQ8
VSSQ7
VSSQ6
VSSQ5
VSSQ4
VSSQ3
VSSQ2
VSSQ1
VSSDL
VDDL
VDD5
VDD4
VDD3
VDD2
VDD1
DQ10
DQ12
DQ13
DQ14
DQ15
DQ11
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A10/AP
A12
BA1
BA0
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CK
CK
CKE
CS
WE
RAS
CAS
LDM
UDM
ODT
LDQS
LDQS
UDQS
UDQS
VREF
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
NC
NC
NC
NC
NC
NC
VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VSSR_MEM_ST_A0
VSSR_MEM_ST_A1
MEM_IO2.5_3
MEM_IO2.5_2
MEM_IO2.5_1
VDDRH0
VSSRH0
MPVSS
PESD_2
MEMTEST
MVREFD
TEST_YCLK
DQA15
DQMA#1
MAA15
WEA#
DQA14
MAA14
DQA13
MAA13
DQA12
MAA12
DQA11
MAA11
DQA10
MAA10
DQA9
MAA9
DQA8
MAA8
DQA7
MAA7
DQA6
MAA6
DQA5
MAA5
DQA4
MAA4
DQA3
MAA3
DQA2
MAA2
DQA1
MAA1
DQA0
MAA0
CASA#
RASA#
DQMA#0
QSA0
ODTA
QSA1
CLKA
QSA0#
CKEA
QSA1#
CLKA#
(5/14 SDRAM)
CSA#
(DIGITAL PCB)
FROM/TO POWER3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3.3
3.3
1.0
0
0
1.8
1.8
0
0
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
2.5
2.5
2.5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
0
1.8
1.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0