45
LC-22LE250
LC-24LE250
CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in
a source synchronous fash-ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.5V ± 0.075V
power supply and 1.5V ± 0.075V VDDQ. The 1Gb DDR3 G-die device is available in 78ball
FBGAs(x4/x8).
Table 13: Absolute Maximum DC Ratings
8. 2Gbit (256M x 8 bit) NAND Flash Memory
H27U2G8F2CTR-BC
a) Key Features
DENSITY
-2Gbit: 2048blocks
Nand FLASH INTERFACE
-NAND Interface
-ADDRESS / DATA Multiplexing
SUPPLY VOLTAGE
-Vcc = 3.0/1.8V Volt core supply voltage for Program,
Erase and Read operations.
MEMORY CELL ARRAY
-X8: (2K + 64) bytes x 64 pages x 2048 blocks
-X16: (1k+32) words x 64 pages x 2048 blocks
PAGE SIZE
-X8: (2048 + 64 spare) bytes
-X16:(1024 + 32spare) Words
Block SIZE
-X8: (128K + 4K spare) bytes
-X16:(64K + 2K spare) Words
PAGE READ / PROGRAM
-Random access: 25us (Max)
-Sequential access: 25ns / 45ns (3.0V/1.8V, min.)
-Program time(3.0V/1.8V): 200us / 250us (Typ)
Содержание LC-24LE250V-BK
Страница 12: ...12 LC 24LE250 LC 22LE250 DIMENSIONS English 20 Dimensional Drawings LC 22LE250 ...
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Страница 18: ...18 LC 24LE250 LC 22LE250 1 1 General Block Diagram 15 General Block Diagram ...
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