– 39 –
MD-MX30/MX30W
Figure 39 SCHEMATIC DIAGRAM (3/13)
7
8
9
10
11
12
R1512
47
C1505
0.047
R1526
6.8K
R1510
1K
TP1501
TP1502
TP1503
TP1504
TP1505
TP1506
Q1501
UN2214
C1503
0.33
L1502
4.7
µ
H
R1511
8.2K
C1502
330P(CH)
C1501
1
C1803
100/10
C1804
2.2
Q1806
UN221 N
R1808
1.8K
Q1803
UN221 N
Q1805
2SA1314 C
R1805
270
C1802
10
R1708
1K
Q1701
UN2213
R1712
27K
Q1702
2SA1162 G
R1714
12
R1711
12
C1714
1
802
6K
803
K
R1811
1
R1804
390
Q1804
A1242 Y
R1806
1
R1809
1
R1807
27K
IC1801
XC62EP32
OLTAGE REGULATOR
5
4
3
2
1
C1805
1
TP1702
TP1533
TP1532
TP1531
TP1530
L1554
0.47
µ
H
L1552
0.47
µ
H
L1551
0.47
µ
H
1
2
3
4
5
6
7
8
17
18
19
20
21
22
23
25
26
27
28
CN1501
C1741
820P
C1750
820P
C1716
47/4
TP1706
TP1704
C1704
47/4
R1716
100K
TP1705
IC1701
UDA1347
AD/DA CONVERTER
TP1703
R1709
39K
R1706
39K
R1710
680K
R1707
1M
C1712
10/16
C1710
10/16
C1702
0.001
C1711
47/4
C1715
0.1
C1708
0.01
C1709
0.01
R1702
0K
1
R1705
820
Q1700
2SD601 AR
IC1702
NJM431U
REGULATOR
3
1
C1707
1
R1703
1K
R1704
3.3K
TP1701
L1702
10
µ
H
L1701
10
µ
H
0
R1529
220
IC1202
IX2474AF
4MBIT D-RAM
C1203
1
TP1214
C1210
22P (CH)
14
R1217
150
XL1201
3.8688MHz
C1209
12P(CH)
R1215
1M
TP1513
TP1514
TP1515
TP1516
TP1517
TP1518
TP1507
TP1508
TP1509
TP1510
TP1511
TP1512
TP1519
TP1520
TP1521
TP1522
TP1523
TP1524
TP1525
TP1526
R1532 3.3K
R1534 1K
R1533 1K
R1535 1K
R1536
1K
R1537
220
R1538
220
R1521
120
R1539
120
C1509
100P (CH)
C1506
100P (CH)
R1516
1.8K
R1515
1.8K
R1517
47
R1518
47
R1513
8.2K
L1501
1
µ
H
LOADIN
P.GND
CW1502
CNS7
CNP7
CDLRCK
CDBCK
CDDATA
GND
CW1501
PCONT0
DIGOUT
GND
DIGIN
RESET
MD-ST
LOAD SW
DSCK
SERCH
KDATA
MDDATA
DSTB
D.GND
D.GND
D.GND
D.GND
DVDD
DVDD
BACKUP
PDOWN
AA.GND
AVCC
R OUT
L OUT
AD.GND
L IN
AA.GND
R IN
BACKUP
VSSA
VDDA
VINL
VREFA
VINR
VADCN
VADCP
MP1
VDDD
VSSD
MP4
BCK
WS
DATAO
DATAI
MP5
MC2
AVSS
AVDD
VOUTR
VDDO
MC1
MP2
MP3
SYSCLK
VSSO
VREFD
VOUTL
CKUP
GND
AA.GND
AA.GND
DIN
DOUT
I/O1
GND
OE
VCC
RAS
A2
A3
A5
CAS
A1
I/O2
A6
I/O4
A8
A4
A9
WE
A7
A0
I/O3
A6
A4
A5
A7
A8
NC
NC
NC
AA.GND
D.GND
PDOWN
A9
A0
A1
A2
A3
C1206
0.0012
R1212
47
20
19
18
17
16
15
14
13
12
11
10 9
8
7
6
5
4
3
2
1
DADATA
ADDATA
LRCK
BCLK
DFCK
C1713
0.01
L3DATA
28 27 26 25 24 23 22 21 20 19 18 17 16 15
C1703
0.1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C1706
0.01
C1705
0.1
2
BACKUP
R1520
47K
R1523
47K
R1527
47K
C1507
0.047
STID
DSTB
MDDATA
DSCK
KDATA
SERCH
RESET
DFCK
BCLK
LRCK
ADDATA
DADATA
L3MODE
L3CLK
4
3
2
1
4
3
2
1
4
3
2
1
CN1502
+B
+B
+B
+B
+B
24
16
15
14
13
12
11
10
9
1
2
3
1
1
2
2
2
3
1
3
3
24
1.2V
2.5V
1.3V
1.7V
1.3V
2.2V
2.4V
1.2V
1.1V
0V
3.2V
1.2V
2.4V
0.8V
1.8V
1.5V
2V
3V
1.1V
1.1V
0V
3.2V
1.4V
1.5V
1.4V
0V
3.2V
0V
0V
3.2V
0V
1.5V
3.17V
3.17V
1.6V
0V
1.57V
3.2V
1.57V
3.2V
0V
0V
0V
1V
0V
3.17V
1.55V
3.17V
3.1V
0V
3.2V
5V
0V
2.46V
0V
3.85V
MD SIGNAL
RECORD SIGNAL
P47 12 - C
TO CD SERVO
PWB
CNPU04
P42 4,5 - H
TO MAIN PWB
• The numbers
1
to
24
are waveform numbers shown in page 66 and 67.