Sharp Aquos LC-32LD166K, Руководство по обслуживанию

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LC-32LD164
LC-32LD165
LC-32LD166
Register. 2176 8
Page size 2176 bytes
Block size (128K 8K) bytes
• Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy
• Mode control
Serial input/output Command control
• Number of valid blocks
Min 1004 blocks Max 1024 blocks
‧
• Power supply VCC = 2.7V to 3.6V
• Access time Cell array to register 25 μ s max Serial Read Cycle 25 ns min (CL=50pF)
• Program/Erase time
Auto Page Program 300 μ s/page typ. Auto Block Erase 2.5 ms/block typ.
• Operating current
Read (25 ns cycle) 30 mA max.
Program (avg.) 30 mA max
Erase (avg.) 30 mA max
Standby 50
μ A max
• Package TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)
•
8 bit ECC for each 512Byte is required.
7.4. U414 (74HC4052PW)
General Description
The 74HC4052 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4052B. The device is specified in
compliance with JEDEC standard no. 7A. The 74HC4052 is a dual 4-channel analog multiplexer/demultiplexer with common
select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to nY3) and a common input/output (pin nZ). The
common channel select logics include two digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When
pin E = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0 and S1. When pin E = HIGH, all
switches are in the high-impedance OFF-state, independent of pins S0 and S1. VCC and GND are the supply voltage pins for
the digital control inputs (pins S0, S1 and E). The VCC to GND ranges are 2.0 V to 10.0 V for the 74HC4052.The analog
inputs/outputs (pins nY0 to nY3 and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC − VEE
may not exceed 10.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground).
Features
♦ Wide analog input voltage range from − 5 V to +5 V
♦ Low ON resistance:
‧
80
Ω
(typical) at VCC − VEE = 4.5 V
‧
70
Ω
(typical) at VCC − VEE = 6.0 V
‧
60
Ω
(typical) at VCC − VEE = 9.0 V
♦ Logic level translation: to enable 5 V logic to communicate with
±
5 V analog signals
♦ Typical ‘break before make’ built-in
♦ Complies with JEDEC standard no. 7A
♦ ESD protection:
‧
HBM JESD22-A114F exceeds 2000 V
‧
MM JESD22-A115-A exceeds 200 V
♦ Specified from
−
40
°
C to +85
°
C and
−
40
°
C to +125
°
C
Applications
♦ Analog multiplexing and demultiplexing
♦ Digital multiplexing and demultiplexing
♦ Signal gating
7.5. U601 (TAS5721)
General Description
The TAS5721 is an efficient, digital-input audio amplifier for driving 2.0 speaker systems configured as a bridge tied load (BTL),
2.1 systems with two satellite speakers and one subwoofer, or in PBTL systems driving a single speaker configured as a parallel
bridge tied load (PBTL). One serial data input allows processing of up to two discrete audio channels and seamless integration
to most digital audio processors and MPEG decoders. The device accepts a wide range of input data formats and sample rates.
A fully programmable data path routes these channels to the internal speaker drivers.