
11
Date Code 20200326
SEL Application Guide 2020-04
Because Zone 3 remains deasserted, Relay 2 does not send a block signal to Relay 1, and Zone 2
starts TIMER 2. If Zone 2 asserts for longer than the programmed timer delay (CTD) in TIMER 2,
the top input of AND 2 becomes true. If the top input of AND 2 is true and Relay 2 has not
received a block from the remote end, Relay 2 issues a trip. In this scenario, both relays identify
the fault in their respective Zone 2 and do not receive a block signal from the remote end, which
allows both relays to trip their respective breakers and clear the line at a high speed.
As another example, consider a fault at Point F2 (see
). In this scenario, Zone 2 at Relay 1
asserts, and Zone 3 remains deasserted. Again, Relay 1 does not send a block signal to Relay 2,
and Zone 2 starts TIMER 1. At Relay 2, Zone 2 desserts, Zone 3 asserts, and the assertion of
Zone 3 sends a block to Relay 1. This causes AND 1 to prevent a high-speed trip. At Relay 2, even
though Relay 1 does not send a block signal, Zone 2 remains deasserted, which causes AND 2 to
prevent a high-speed trip.
NOTE:
This section provides an overview of DCB schemes. For a more in-depth discussion, refer to [2].
DCB S
ETUP
To setup a DCB scheme in the SEL-421-5, SEL-311L, or SEL-321-1 relays, you must enable the
logic in the relays. The settings in the relays are similar.
provide a
summary of how to set up the DCB logic in the SEL-421-5, SEL-311C-1, and SEL-321-1, respec-
tively. These settings only apply to directional starting. This application guide does not discuss
nondirectional starting.
Figure 11
Simplified DCB Logic
Zone 2
TRIP
Block
Receiver
Block
Transmitter
Zone 2
TRIP
Block
Receiver
Block
Transmitter
Relay 1
Relay 2
CTD
AND 1
Zone 3
AND 2
Zone 3
CTD
TIMER 1
TIMER 2
Table 11
SEL-421-5 DCB Settings
Setting
Setting Description
Setting Value
Description
ECOMM
Communication-Assisted Trip
Scheme
DCB
Enables the DCB logic in the SEL-421-5.
Z3XPU
Zone 3 Reverse Pickup Time
Delay
1 (default)
Current reversal guard pickup timer.
Z3XD
Zone 3 Pickup Extension Time
Delay
6 (default)
Prevents a DCB scheme misoperation during current
reversal.
BTXD
Block Trip Receive Extension
Delay
1
Sets the reset time of a block trip received condition
after the reset of a block trip input.
21SD
Zone 2 Phase and Ground Coor-
dination Time Delay
See
Delays the M2P and Z2G element outputs.
67SD
67G and 67Q Coordination
Time Delay
See
Delays the 67N2 element output.