SBC-C61
SBC-C61 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.1 - Author: S.B. - Reviewed by N.P. - Copyright © 2021 SECO S.p.A.
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3.3.8
MIPI-CSI2 Connector
NXP iMX8M Mini Processor includes an Image Processing Subsystem, that can be
used for video applications, like video-preview, video recording and frame grabbing.
It is possible to access to the video input port through an FFC/FPC connector, type
HIROSE p/n FH12-18S-0.5SH(55) which is able to accept 18 poles 0.5mm pitch FFC cables.
CAM0_ENA#: Camera enable output, active low signal, electrical level VDD_1V8
CAM0_RST#: Camera Reset output, active low signal, electrical level VDD_1V8
I2C_CAM0_SCL: I2C Bus clock line. Bidirectional signal, electrical level VDD_1V8 with a 2K2
Ω
pull-up
resistor. It is managed by the processor
’
s I2C controller #2.
I2C_CAM0_SDA: I2C Bus data line. Bidirectional signal, electrical level VDD_1V8 with a 2K2
Ω
pull-up
resistor. It is managed by the processor
’
s I2C controller #2.
MIPI_CSI_D0_P/ MIPI_CSI_D0_N: MIPI CSI Port differential data pair #0.
MIPI_CSI_D1_P/ MIPI_CSI_D1_N: MIPI CSI Port differential data pair #1.
MIPI_CSI_D2_P/ MIPI_CSI_D2_N: MIPI CSI Port differential data pair #2.
MIPI_CSI_D3_P/ MIPI_CSI_D3_N: MIPI CSI Port differential data pair #3.
MIPI_CSI_CLK_P/ MIPI_CSI_CLK_N: MIPI CSI Port differential clock pair.
When connecting CSI cameras to CN16 connector, it is strongly recommended to use shielded cable for EMC compatibility.
MIPI-CSI2 connector CN16
Pin Signal
Pin Signal
1
MIPI_CSI_D3_N
10
MIPI_CSI_D0_N
2
MIPI_CSI_D3_P
11
MIPI_CSI_D0_P
3
MIPI_CSI_D2_N
12
GND
4
MIPI_CSI_D2_P
13
CAM0_ENA#
5
MIPI_CSI_D1_N
14
N.C.
6
MIPI_CSI_D1_P
15
I2C_CAM0_SCL
7
MIPI_CSI_CLK_N
16
I2C_CAM0_SDA
8
MIPI_CSI_CLK_P
17
CAM0_RST#
9
GND
18
+3.3V_AUX
