Q7-C72
Q7-C72 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Authors: A.R - Reviewed by M.B. - Copyright © 2021 SECO S.p.A
29
3.2.6
USB interface signals
The module µQ7-C72 with NXP i.MX 8M Mini family of processors has up to 5x USB ports consisting of 1x USB 2.0 OTG port from the NXP i.MX 8M Mini processor
USB controller, and 4x USB 2.0 host ports coming from a Microchip USB 2514B-AEZC USB 2.0 hub controller.
When configured with NXP i.MX 8M Nano family of processors, µQ7-C72 has only 4x USB 2.0 host ports, and the USB1 OTG port is not available.
Here following the signals related to USB interfaces.
USBP0+/USBP0-: Universal Serial Bus Downstream Port #1 differential pair (coming out from USB 2.0 hub controller).
USBP1+/USBP1-: Universal Serial Bus Port #1 differential pair (coming out from NXP i.MX 8M Mini processors USB 2.0 controller).
USBP2+/USBP2-: Universal Serial Bus Downstream Port #2 differential pair (coming out from USB 2.0 hub controller).
USBP3+/USBP3-: Universal Serial Bus Downstream Port #3 differential pair (coming out from USB 2.0 hub controller).
USBP4+/USBP4-: Universal Serial Bus Downstream Port #4 differential pair (coming out from USB 2.0 hub controller).
USB_ID: USB ID Input This signal must be driven as an open collector signal by external circuitry placed on the carrier board. It must be tied to GND when USB Port
#1 has to be set to work in Host mode. When not driven, USB Port#1 will work in Client mode.
USB_VBUS: USB Client Connect Pin, electrical level +5V_ALW. When USB Port #1 is set to work in Client mode, then this signal shall be used to inform the USB
controller when an external USB Host is connected (signal High) or disconnected (Signal Low)
USB_OTG_PEN: USB Power enable pin for USB Port 1, electrical level +3.3V_RUN. This pin Enables the Power for the USB-OTG port on the carrier board.
For EMI/ESD protection, common mode chokes on USB data lines, and clamping diodes on USB data and voltage lines, are also needed.
3.2.7
SDIO interface signals
The NXP i.MX 8M Mini and Nano processors include an Ultra Secured Digital Host Controller (uSDHC), providing the interface between the host system and an SD
/ SDIO/ MMC card interface.
Such an SD controller complies with SD Host Controller Standard Specification version 2.0 / 3.0, with MMC System Specifications version up to 5.1, with the SDIO
Card Specifications version 2.0 / 3.0.
The SD port is externally accessible through the golden edge finger connector, and can work in 1-bit and 4-bit mode.
Signals involved with SD interface are the following:
SDIO_PWR#: SD power enable. Active Low Output signal, electrical level +3.3V_RUN with 10k pull-up resistor. This signal can be used on the Carrier board to
enable the power line for the SD card.
SDIO_CD#: Card Detect Input. Active Low Signal, electrical level +3.3V_RUN with 100k pull-up resistor. This signal must be externally pulled low to signal that a
SD Card Device is present.
