Q7-C72
Q7-C72 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Authors: A.R - Reviewed by M.B. - Copyright © 2021 SECO S.p.A
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3.2.3
PCI Express interface signals
The µQ7-C72 module can offer one PCI Express x1 lane, which is directly managed by i.MX8 Mini processor.
Note that this interface is only made available with by i.MX8 Mini family of processors.
PCI express Gen 2.0 (5Gbps) is supported.
Here following the signals involved in PCI express management:
P/PCIE0_RX-: PCI Express lane #0, Receiving Input Differential pair
P/PCIE0_TX-: PCI Express lane #0, Transmitting Output Differential pair
PCIE_/PCIE_CLK_REF-: PCI Express Reference Clock, Differential Pair
PCIE_RST#: Reset Signal that is sent from Qseven
®
Module to any PCI-e device available on the carrier board. It is a +3.3V_RUN active-low signal; it can be used
directly to drive externally a single RESET Signal. In case there is the need to supply Reset signal to multiple devices, it is recommended to provide for a buffer on the
carrier board.
PCIE_WAKE#: Wake up Signal that is asserted from any PCI-e device available on the carrier board to Qseven
®
Module. It is a 3V3_RUN active-low signal with a
-up resistor.
3.2.4
UART interface signals
According to Qseven
®
Rel. 2.1 specifications, µQ7-C72 offers one UART interface, directly managed by i.MX8 Mini and Nano processor (all versions).
Here following the signals related to UART interface:
UART0_TX: UART Interface, Serial data Transmit (output) line, +3.3V_RUN electrical level.
