Q7-928
Q7-928 User Manual - Rev. First Edition: 1.0 - Last Edition: 3.0 - Author: S.B. - Reviewed by P.Z Copyright © 2016 SECO S.r.l.
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3.2
Connectors description
3.2.1
FFC/FPC Camera Interface
NXP i.MX6 Processor includes an Image Processing Subsystem, that can be used for video
applications, like video-preview, video recording and frame grabbing.
The access to the video input port comes through an FFC/FPC connector, type HIROSE p/n
FH12A-36-S-0.5SH(55), which is able to accept 36 poles 0.5mm pitch FFC cables.
On the same connector are carried:
-
a 10-bit parallel port, supporting ITU-R BT.656 and so on, managed by i.MX6
CSI2IPU gasket.
-
MIPI CSI (Camera Serial Interface) Port.
Both video inputs can work independently and simultaneously.
For i.MX6 Solo and Dual Lite processors, CSI port is limited to 2 lanes only.
Here following is shown the meaning of various pins of the connector.
Pins[1÷17]: 8-bit parallel format arranged to guarantee 8-bit alignment LSB for ITU BT-656
format; voltage level: +3.3V_CAM.
Pins[18÷19]: additional pins for 10-bit format; voltage level: +3.3V_CAM.
Pins[22÷25]: GPIO/CAM I2C; voltage level: +3.3V_CAM
Pins[29÷30]: +3.3V_CAM
Pins [31÷36]: MIPI CSI first channel (Clock+2 lanes)
Pins [20÷21; 27÷28]: MIPI CSI additional lanes (only for i.MX6 Dual and i.MX6 Quad)
CAMERA CONNECTOR - CN2
Pin
Signal
Pin
Signal
1
CAM_XCLK_A
19 CSI0_DAT11
2
GND
20 CSI0_D2_DN
3
---
21 CSI0_D2_DP
4
GND
22 CAM_GPIO_A
5
CAM_PCLK
23 GP0_I2C_CLK
6
CAM_VS
24 GP0_I2C_DAT
7
CAM_HS
25 CAM_RESETB
8
CAM_FLD
26 GND
9
GND
27 CSI0_D3_DN
10 CSI0_DAT12
28 CSI0_D3_DP
11 CSI0_DAT13
29 +3.3V_CAM
12 CSI0_DAT14
30 +3.3V_CAM
13 CSI0_DAT15
31 CSI0_CLK0_DN
14 CSI0_DAT16
32 CSI0_CLK0_DP
15 CSI0_DAT17
33 CSI0_D0_DN
16 CSI0_DAT18
34 CSI0_D0_DP
17 CSI0_DAT19
35 CSI0_D1_DN
18 CSI0_DAT10
36 CSI0_D1_DP
