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© Sealevel Systems, Inc.
3612 Manual | SL9115 9/2021
Technical Description
The
PC-ACB.MP
utilizes the Zilog 85233
E
nhanced
S
erial
C
ommunications
C
ontroller (ESCC). This chip
features programmable baud rate, data format and interrupt control. Refer to the ESCC
User’s Manual
for
details on programming the 85233 ESCC chip.
Features
•
One channel of synchronous or asynchronous communications using the Zilog Z85233 chip
•
Programmable electrical interface selection EIA/TIA-232/530/530A/485 and ITU V.35
•
Programmable options for Transmit clock as input or output
•
Software programmable baud rate
Internal Baud Rate Generator
The baud rate of the ESCC is programmed under software control.
Control and Status Registers Definition
The control and status registers occupy 16 consecutive locations. The following tables provide a functional
description of the bit positions. X = do not care
Base
Mode
D7
D6
D5
D4
D3
D2
D1
D0
+4
RD
0
IRQST
0
0
0
0
0
DSRA
+4
WR
X
X
X
X
X
X
X
X
+5
RD
485CLK
ECHOA
SYNCA_RTS
SYNCA_CTS
AM3
AM2
AM1
AM0
+5
WR
485CLK
ECHOA
SYNCA_RTS
SYNCA_CTS
AM3
AM2
AM1
AM0
+6
RD
0
0
0
0
RLA
LLA
TSETSLA
RXCOPTA
+6
WR
X
X
X
X
RLA
LLA
TSETSLA
RXCOPTA
+7
RD
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0