Schweitzer Engineering SEL-351P, Быстрый старт

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Date Code 990215 Trip and Target Logic 5-3
SEL-351P Manual Técnico
Set Trip
Refer to Figure SECTION 5: .1. All trip conditions:
•
Communications-Assisted Trip
•
Direct Transfer Trip
•
Switch-Onto-Fault Trip
•
Other Trips
are combined into OR-1 gate. The output of OR-1 gate asserts Relay Word bit TRIP to logical 1,
regardless of other trip logic conditions. It also is routed into the Minimum Trip Duration Timer
(setting TDURD).
As shown in the time line example in Figure SECTION 5: .2, the Minimum Trip Duration Timer
(with setting TDURD) outputs a logical 1 for a time duration of “TDURD” cycles any time it
sees a rising edge on its input (logical 0 to logical 1 transition), if it is not already timing (timer is
reset). The TDURD timer assures that the TRIP Relay Word bit remains asserted at logical 1 for
a minimum of “TDURD” cycles. If the output of OR-1 gate is logical 1 beyond the TDURD
time, Relay Word bit TRIP remains asserted at logical 1 for as long as the output of OR-1 gate
remains at logical 1, regardless of other trip logic conditions.
The Minimum Trip Duration Timer can be set no less than 4 cycles.
Figure SECTION 5: .2: Minimum Trip Duration Timer Operation (see bottom of
Figure SECTION 5: .1)