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IC BLOCK DIAGRAM & DESCRIPTION
IC820 ZR36732 (MPEG)
SDRAM In terface (35 pins).
90
87
84
81
78
75
72
68
70
74
76
79
82
85
88
91
RAMDAT[15]
RAMDAT[14]
RAMDAT[13]
RAMDAT[12]
RAMDAT[11]
RAMDAT[10]
RAMDAT[9]
RAMDAT[8]
RAMDAT[7]
RAMDAT[6]
RAMDAT[5]
RAMDAT[4]
RAMDAT[3]
RAMDAT[2]
RAMDAT[1]
RAMDAT[0]
3-S
I/O (r.t.)
Reset: input (p.d.)
Standby: 3-S (p.d.)
SDRAM bidirectional data bus.
55
53
54
51
48
46
43
41
42
45
47
50
RAMADD[11]
RAMADD[10]
RAMADD[9]
RAMADD[8]
RAMADD[7]
RAMADD[6]
RAMADD[5]
RAMADD[4]
RAMADD[3]
RAMADD[2]
RAMADD[1]
RAMADD[0]
O
O (p.d.)
Reset: output
Standby: 3-S
SDRAM address bus output.
60
RAMRAS#
O
O (p.u.)
Reset: output
Standby: 3-S (p.u.)
SDRAM row select output.
61
RAMCAS#
O
O (p.u.)
Reset: output
Standby: 3-S (p.u.)
SDRAM column select output.
66
PCLK
O
O (p.d.)
Reset: output
Standby: 3-S
SDRAM clock output (Same as internal processing clock).
64
RAMDQM
O
O (p.d.)
Reset: output
Standby: 3-S (p.u.)
SDRAM data masking output.
57
RAMCS0#
O
O (p.u.)
Reset: output
Standby: 3-S (p.u.)
SDRAM chip select output for the lower (or only) 2MB device (16Mbit).
59
RAMCS1#
O
O (p.u.)
Reset: output
Standby: 3-S (p.u.)
SDRAM chip select output for the upper 2MB device (16Mbit).
62
RAMWE#
O
O (p.u.)
Reset: output
Standby: 3-S (p.u.)
SDRAM write enable output.
Pin
Name
Type
Direct io n
Status Afte r RESET/
During STANDBY
Test Signal In terface (3 pins).
125
SCNENBL
I
I
Input
Production test pin (connected directly to GNDP in normal operation).
129
TESTMODE
I
I
Input
In normal operation this pin must be connected directly to GNDP.
112
ICEMODE#
I
I
Input
In normal operation this pin must be connected directly to VDDP. If it is asserted, then the ADP goes into ICE mode. In
this mode 4 of the Decoder pins turn into ICE interface pins:
HD
[11] = TCK ó ICE interface clock
HD
[10] =TMS ó IC E interface mode select input
HD
[9] = TDO ó IC E interface data output
HD
[8] = TDI ó ICE interface data input
Power Signals (49 pi ns ).
*
GNDP
(* pins 10, 40, 49, 56, 65, 69, 80, 86, 97,
128, 146)
Digital ground of 3.3 V supply.
*
V
DDP
(* pins 3, 16, 19, 26, 38, 44, 52, 58, 67, 71,
77, 83, 89, 94, 98, 99, 126, 135, 140)
3.3 V Digital power supply.
132
GNDP-A2
Digital ground of filtered 3.3 V supply for
AMCLK
.
130
VDDP-A2
3.3 V filtered digital power supply for
AMCLK
.
*
GNDC
(* pins 14, 35, 73, 114, 144)
Digital ground of 1.8 V supply.
*
V
DDC
(* pins 12, 33, 63, 116, 142)
1.8 V Digital power supply.
123
GNDA
Ground plane of internal PLL circuit.
121
VDDA
1.8 V Power supply for internal PLL circuit.
104
VDDDAC
3.3 V Analog power supply for the DACs.
101
107
109
110
GNDDAC_D
GNDDAC_B
GNDDAC_P
GNDDAC_S
Grounds for the DACs 3.3 V analog power supply
Pin
Name
Type
Direct io n
Status Afte r RESET/
During STANDBY
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
- RA
10
, Column address : CA
0
- CA
7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latchea column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Mskes data output Hi-Z, I
SHZ
sfter the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
Pin
CLK
CS
CKE
A
0
- A
10/
AP
BA
RAS
CAS
WE
L(U)DQM
DQ
0
-
15
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C/RFU
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Dsta Output Power/Ground
No Connection/
Reserved for Furure Use
Programming Register
Timing Register
Latency & Borst Length
Column Decoder
Data Input Register
Output Buf
fer
Row Decoder
LRAS
LCBR
Bank Select
LRAS
LCAS
LDQM
LWCBR
LCBR
LWE
Row Buf
fer
Refresh Counter
Col. Buf
fer
Address Register
I/O Control
512K x 16
512K x 16
35
20~24,
27~32
2,3,5,6,7,8,9,11,
12,39,40,42,43,
45,46,48,49
35
34
18
17
16
15
36
14
Sense AMP
CLK
ADD
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
DQ1
LDQM
LWE
LCKE
IC821 K4S16162D
(512 X 16Bit X 2 Bank synchronous DRAM )
NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger inout, 5V tolerant. (3) Tri-state output.
PIN ASSIGNMENTS
Output Amp and
Low-pass Filter
Output Amp and
Low-pass Filter
Output Amp and
Low-pass Filter
Output Amp and
Low-pass Filter
Output Amp and
Low-pass Filter
Output Amp and
Low-pass Filter
DAC
DAC
DAC
DAC
DAC
DAC
4x / 8x
Oversampling
Digital Filter
with
Function
Controller
Enhanced
Multi-level
Delta-Sigma
Modulator
Serial
Input
I/F
Function
Control
I/F
System Clock
Manager
System Clock
Zero Detect
Power Supply
38
33
34
35
36
37
42
47
46
45
41
40
BCK
TEST
14 V
OUT
1
V
OUT
2
V
OUT
3
V
COM
V
OUT
4
V
OUT
5
V
OUT
6
13
12
15
11
10
9
39
SCKO
48
ZEROA
1
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
2
3
4
5
6
V
DD
43
DGND
44
V
CC
1-5
28,26.24
22,18
27,25.23
21,17,19
AGND1-6
RST
ML
MC
MDI
MDO
SCKI
LRCK
DATA1(1,2)
DATA2(3,4)
DATA3(5,6)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
O
O
O
O
O
O
-
-
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
O
I
I
I
I
I
O
I
I
-
-
-
I
I
I
O
NAME
ZERO1/GPO1
ZERO2/PGO2
ZERO3/PGO3
ZERO4/PGO4
ZERO5/PGO5
ZERO6/PGO6
NC
NC
V
OUT
6
V
OUT
5
V
OUT
4
V
OUT
3
V
OUT
2
V
OUT
1
V
COM
NC
AGND5
V
CC
5
AGND6
NC
AGND4
V
CC
4
AGND3
V
CC
3
AGND2
V
CC
2
AGND1
V
CC
1
NC
NC
NC
NC
MDO
MDI
MC
ML
RST
SCKI
SCKO
BCK
LRCK
TEST
V
DD
DGND
DATA1
DATA2
DATA3
ZEROA
DESCRIPTION
Zero Data Flag for V
OUT
1. Can also be used as GPO pin.
Zero Data Flag for V
OUT
2. Can also be used as GPO pin.
Zero Data Flag for V
OUT
3. Can also be used as GPO pin.
Zero Data Flag for V
OUT
4. Can also be used as GPO pin.
Zero Data Flag for V
OUT
5. Can also be used as GPO pin.
Zero Data Flag for V
OUT
6. Can also be used as GPO pin.
No Connection
No Connection
Voltage Output of Audio Signal Corresponding to Rch on DATA3. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA3. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Rch on DAYA2. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA2. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Rch on DATA1. Up to 192kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA1. Up to 192kHz.
Common Voltage Output. This pin should be bypassed with a 10uF capacitor to AGND.
No Connection
Analog Ground
Analog Power Supply, +5V
Analog Ground
No Connection
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
No Connection
No Connection
No Connection
No Connection
Serial Data Output for Function Register Control Port
Serial Data Input for Function Register Control Port
Shift Clock for Function Register Control Port
Latch Enable for Function Register Control Port
System Reset, Active LOW
System Clock In. Input frequency is 128,192,256,384,512, or 768f
s
.
Buffered Clock Output. Output frequency is 128,192,256,384,512, or 768f
s
or one-half of 128,192,256,384,512 or 768f
s
.
Shift Clock Input for Serial Audio Data.
Left and Right Clock Input. This clock is equal to the sampling rate, f
s
.
Test Pin. This pin should be connected to DGND.
Digital Power Supply, +3.3V
Digital Ground for +3.3V
Serial Audio Data Input for V
OUT
1 and V
OUT
2
Serial Audio Data Input for V
OUT
3 and V
OUT
4
Serial Audio Data Input for V
OUT
5 and V
OUT
6
Zero Data Flag. Logical "AND" of ZERO1 through ZERO6.
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
IC870 PCM1602Y (Digital to Analog Controller)
