Sanyo DC-TS730, Руководство по обслуживанию

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IC BLOCK DIAGRAM & DESCRIPTION
IC460,461,470,471,480,481,490,495 KIA4558F,
NJM4558M(Dual Low Noise Operational Amplifier)
IC462,472 LM1876 (Dual 20W audio Power Amplifier)
2
3
4 5
6
8 1
OUT A
-IN A
+IN A
V
EE
V
CC
OUT B
-IN B
+IN B
7
B
A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Vcc B
Standby B
+ In B
- In B
Mute B
GND B
Standby A
+ In A
- In A
Mute A
GND A
V
EE
Out A
V
CC
A
Out B
8
2
3
+In A
7 -In A
Out A Amp A
4
V
EE
5
GND
A
Vcc
A
LM1876
IC482 LM4700TF (30w audio Power Amplifier)
11
10
9
8
7
6
5
4
3
2
1
STANDBY
V
IN
+
V
IN
-
MUTE
GND
NC
NC
V
EE
OUTPUT
NC
V
CC
10
1
3
V
IN
+
9 V
IN
-
OUTPUT
4
V
EE
7
GND
Vcc
LM4700
IC483 LM3876TF (56w audio Power Amplifier)
11
10
9
8
7
6
5
4
3
2
1
NC
V
IN
+
V
IN
-
MUTE
GND
NC
NC (+)
V-
OUTPUT
NC
V+
10
1
3
V
IN
+
9 V
IN
-
OUTPUT
7
GND
4
V-
V+
LM3876
OSC
Serial
Data
Interface
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
30
31
32
33
34
35
36
37
38
42
41
40
39
1
2
3
4
7
6
8
9
5
30 13 11 10
Control
Display Memory
(24 bits x 17 Words)
Key Moter Memory
LED
Driver
Grid
Driver
Segment
Driver
Grid
Driver
Key Scan
Output
Driving Circuit
TI~inc Generator
SG1/KS1
SG2/KS2
SG3/KS3
SG4/KS4
SG5/KS5
SG6/KS6
SG7/KS7
SG8/KS8
SG9/KS9
SG10/KS10
SG11/KS11
SG12/KS12
SG13/KS13
SG14/KS14
SG15/KS15
SG16/KS16
SG17/GR12
SG18/GR11
SG19/GR10
SG20/GR9
SG21/GR8
SG22/GR7
SG23/GR6
SG24/GR5
GR1
GR2
GR3
GR4
LED1
LED2
LED3
LED4
DIN
DOUT
CLK
STB
OSC
VEE GND VDD K2 K1
Description
LED Output Pin
Oscillator Input Pin
A resistor is connected to this pin to
determinc the oscillation frequency
Data Output Pin (N-Channel, Open-Drain)
This pin outputs scrial data at the falling
cdge of the shift clock (starting from the lower bit)
Data Input Pin
This pin inputs serial data at the rising cdge
of the shift clock (starting from the lower bit)
Clock Input Pin
This pin reads serial data at the rising cdge
and outputs data at the falling cdge.
Serial Interface Strobe Pin
The data input after the STB has fallen is
processed as a command.
When this pin "HIGH",CLK is ignored,
Key Data Input Pins
The data inputted to these pins are fatched
at the end of the display cycle.
Logic Ground Pin
Logic Power Supply
High-Voltage Segment Output Pins
Also acts as the Key Source
Pull-Down Level
High Voltage Segment/Grid Output Pins
High-Voltage Grid Output Pins
Pin No.
1 to 4
5
6
7
8
9
10, 11
12, 44
13, 43
14 to 29
30
31 to 38
39 to 42
I/O
O
I
O
I
I
I
I
-
-
O
-
O
O
Pin Name
LED1 to LED4
OSC
DOUT
DIN
(Schmitt Trigger)
CLK
(Schmitt Trigger)
STB
(Schmitt Trigger)
K1 to K2
VSS
VDD
SG1/KS1 to SG16/KS16
VEE
SG17/GR12 to SG24/GR5
GR4 to GR1
IC601 PT6315 (VFD Driver/Controller)
8 VCC
4 GND
7 WP
3 A
2
2 A
1
1 A
0
6 SCL
5 SDA
DEVICE
ADDRESS
COMPARATOR
START
STOP
LOGIC
SERIAL
CONTROL
LOGIC
H.V. PUMP/TIMING
DATA RECOVERV
EEOROM
SERIAL MUX
D
OUT
/ACK
LOGIC
V DEC
DATA WORD
ADDR/COUNTER
R/W
D
IN
D
OUT
LOAD INC
COMP
LOAD
FN
X DEC
IC801 AT24C02N-10SI-2.7 (EEPROM)