Sanyo DC-MCR350M, Руководство по обслуживанию

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IC BLOCK DIAGRAM & DESCRIPTION
1
PRE-
DRIVE
INPUT LOGIC CIRCUIT
5
4
6
10 9 7 2 8 3
GND
IN1
OUT1 P1
VCC2 OUT2 P2
VZ
VCC
IN2
IC150 LB1641L (Bidirectional Motor Driver)
Input Output Action
Brake
Normal(Reverse)Rotary
Reverse(Normal)Rotary
Brake
IN1
0
1
0
1
IN2
0
0
1
1
OUT1
0
1
0
0
OUT2
0
0
1
0
SRAM/ROM
Interface
GPIO
Interface
Gateway
DMA Controller
Huffman
Decoder
Video
Processor
32-bit
RISC Processor
TV-Encoder
DRAM
Interface
OSD
Display
Controller
TDM
Interface
Transport
Parser
Serial Audio
Interface
Audio
ADC
8kB cache
1
38 39
6465
102
103 128
A
UX2[3]/IRQ
A
UX2[4]/C2P0
A
UX2[5]/SP
A
UX2[6]/S0S1
A
UX2[7]
A
UX1[0]
A
UX1[1]
A
UX1[2]
A
UX1[3]
A
UX1[4]
A
UX1[5]
A
UX1[6]/VFD_DO
A
UX1[7]/VFD_DI
VCC
VSS
A
UX0[0]
A
UX0[1]
A
UX0[2]
A
UX0[3]
A
UX0[4]
VSSV VSSV VD
A
C
YD
A
C
VCCV VCCV
VPP DRAS1# CAS# MCLK SEL_PLL0/TSD SEL_PLL1/TWS TBCK TDMCLK TDMDR TDMFS LA19 LA18 LA17 LA16 LA15 LA14 LA13 LA12 LA11 LA10 LA9 LA8 VCC VSS LA7 LA6
VSSA
RSEVT
VREF
COMP
VCM
MIC2
MIC1
VDDA
VSSA
AUX0[5]
AUX0[6]
AUX0[7]
AUX3[0]
AUX3[1]
AUX3[2]
LWR#
LOE#
CS0#
CS1#
CS3#
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
VCC
XIN
XOUT
VSS
LA0
LA1
LA2
LA3
LA4
LA5
AUX2[2]/SQCK
AUX2[1]/SQSO
AUX2[0]/VFD_CLK
VCC_P
VSS_P
VSS
RESET#
VCC
DBUS15
DBUS11
DBUS13
DBUS12
DBUS11
DBUS10
DBUS9
DBUS8
DBUS7
DBUS6
DBUS5
DBUS4
DBUS3
DBUS2
DBUS1
DBUS0
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
DOE#/MA9
DWE#
DRAS0#
VCC
VSS
Names Pin No. I/O Descriptions
VSSA 1.9 G Ground for analog circuits.
RSET 2 O
Reset. Internal current source generator. Connect this pin to
a 510
Ω
resistor to ground.
VREF 3 O
Output reference voltage. Connect to a 0.01-
µ
F high -frequency
bypass capacitor to VSSA.
COMP 4 O
Compensation capacitance for low-pass filter on VDAC. Connect
to a 0.01-
µ
F high-frequency bypass capacitor to VSSA.
VCM 5 O
ADC analog voltage reference. Connect to a 0.01-
µ
F filter
capacitor to VSSA.
MIC1.MIC.2 6,7 I Microphone inputs.
VDDA 8 P 5.0V power supply for analog circuits.
AUX0[7:5] 10:12 I/O General-purpose programmable I/O.
AUX3[2:0] 13:15 I/O General-purpose programmable I/O.
LWR# 16 O RISC interface Write Enable (active-low).
LOE# 17 O RISC SRAM Output Enable (active-low).
CS0# 18 O Chip select 0 for SRAM (active-low).
CS1# 19 O Chip select 1 for SRAM (active-low).
CS3# 20 O Chip select 3 for SRAM (active-low).
LD[7:0] 21:28 I/O Data bus.
VCC 29.42.66.95.116 P Core power supply (2.5V).
XIN 30 I Crystal connection or input source of 27MHz. Must be 50% duty cycle.
XOUT 31 O Crystal connection or output drive of an input clock source.
VSS 32,41,65,97,117 G Ground for core.
LA[19:0] 33:40,43:54 O Address bus.
TDMFS 55 I Frame signal from CDROM.
TDMDR 56 I Data signal from CDROM.
TDMCLK 57 I Clock signal from CDROM.
TBCK 58 O Transmit clock when sending audio IIS data to external DAC.
SEL_PLL1 I
PLL mode select 1. Pulldown to ground to bypass PLL. Pullup to
VCC for optimal performance.
TWS O Audio strobe signal of IIS signals to external DAC.
SEL_PLL0 I
PLL mode select 0. Pulldown to GND to bypass PLL. Pullup to VCC
for optimal performance.
TSD O Audio data of IIS signals to external DAC.
MCLK 61 I/O
Media clock input to drive external audio devices or media clock
output when driven by external source into the ES 3890.
CAS# 62 O Column Address Strobe to DRAM (active-low).
DRAS1# 63 O Row Address Strobe 1 to DRAM (active-low).
VPP 64 P 5V power supply.
DRAS0# 67 O Row Address Strobe 0 to DRAM (active-low).
DWE# 68 O Write Enable to DRAM (active-low).
DOE# O Data Out Enable to DRAM (active-low).
MA9 O Multiplexed memory row and column address.
MA[8:0] 70:78 O Multiplexed memory row and column address.
59
60
69
Names Pin No. I/O Descriptions
DBUS[15:0] 79:94 I/O Input when DRAM is being read. Output when DRAM is being written.
REST# 96 I External system reset forces ES3890 to do a reset (active-low).
VSS_P 98 G Ground for system PLL.
VCC_P 99 P 2.5V power supply for system PLL.
AUX2[0] I/O General-purpose programmable I/O.
VFD_CLK I VFD clock
AUX2[1] I/O General-purpose programmable I/O.
SQSO I Subcode-Q data.
AUX2[2] I/O General-purpose programmable I/O.
SQCK I Subcode-Q clock.
AUX2[3] 103 I/O General-purpose programmable I/O.
AUX2[4] I/O General-purpose programmable I/O.
C2PO I C2PO error correction flag from CDROM.
AUX2[5] I/O General-purpose programmable I/O.
SP I Serial port from 16550 UART.
AUX2[6] I/O General-purpose programmable I/O.
S0S1 I Subcode-Q sync.
AUX2[7] 107 I/O General-purpose programmable I/O.
AUX1[5:0] 108:113 I/O General-purpose programmable I/O.
AUX1[6] I/O General-purpose programmable I/O.
VFD_DO O VFD data output.
AUX1[7] I/O General-purpose programmable I/O.
VFD_DI I VFD data input.
AUX0[1:0] 118,119 I/O General-purpose programmable I/O.
AUX0[2] 120 I General-purpose programmable input.
AUX0[3] 121 I/O General-purpose programmable I/O.
AUX0[4] 122 I/O General-purpose programmable input.
VSSV 123,124 G Ground for VDAC circuit.
VDAC 125 O Video DAC V output.
YDAC 126 O Video DAC Y output.
VCCV 127,128 P 2.5V power supply for video DAC circuit.
106
114
115
101
102
104
105
100
IC160 ES3890F (VCD Processor)