SSD P4 (PATA) Solid State Drive
Product Manual
Rev 0.4
© 2010 SanDisk® Corporation
10
Document No. 80-11-XXXX1
1.3
Functional Description
SSD P4 contains a high level, intelligent subsystem. This intelligent (microprocessor)
subsystem provides many capabilities not found in other types of memory cards.
These capabilities include the following:
•
Standard ATA register and command set
•
Support for Trim command
•
S.M.A.R.T. feature supported
•
Host independence from details of erasing and programming flash memory
•
Sophisticated system for managing defects (similar to systems found in
magnetic disk drives)
•
Sophisticated system for error recovery including a powerful error correction
code (ECC)
•
Advanced power management for low power operation
•
Implementation of dynamic and static wear-leveling to extend card’s life
1.4
Defect and Error Management
SSD P4 contains a sophisticated defect and error management system that is similar
to the systems found in magnetic disk drives, and in many cases, offers
enhancements. If necessary, the SSD card will rewrite data from a defective sector
to a good sector. This action is completely transparent to the host and does not
consume any user data space.
The SSD soft error rate specification is much better than the magnetic disk drive
specification. In the extremely rare case that a read error does occur, the SSD P4
products have innovative algorithms to recover the data by using error detection
code and error correction code (EDC/ECC). These defect and error management
systems, coupled with the solid state construction, give SSD P4 unparalleled
reliability.
1.5
Wear Leveling
Wear leveling is an intrinsic part of the erase pooling functionality of SSDs using
NAND memory. Advanced features of dynamic and static wear-leveling, and
automatic block management are used to ensure an even distribution of write erase
cycle throughout the entire device, regardless of how dynamic or static the data
written is. This guarantees high data reliability and maximizes flash life expectancy.
1.6
Bad Block Management
Bad blocks are occasionally created during the life cycle of a flash component, in a
phenomenon called dynamic bad-block accumulation. These bad blocks must be
marked and replaced dynamically in order to prevent read/write failures. When a bad
block is detected, the embedded Bad Block Mapping algorithm maps out the block,
which will be not used for storage anymore.