SPI Protocol Definition
SanDisk Secure Digital (SD) Card Product Manual, Rev. 1.9 © 2003 SANDISK CORPORATION
5-19
The following figure describes stop transmission operation in Multiple Block Write transfer.
CS
L L L L L L L L L L L L L L L L L L L L L L H H H L L L L
<N
WR
-> <1byte-> <N
BR
-> <N
EC
-> <- N
DS
->
Data In
Data Block H H H H H H H H H stop tran
token
H H H X X X H H H H
Data Out
H H H H Data Resp Busy H H H H H H H H H Busy
(1)
L Z Z Z Busy
(1)
H
(1) The Busy may appear within N
BR
clocks after Stop Tran Token. If there is no Busy, the host may continue to the next
command.
Figure 5-18. Stop Transmission Timing—Multiple Block Write
5.4.4. Timing Values
Table 5-5 shows the timing values and definitions. For more information, refer to Table 4-17 in Section 4.0,
Section 5.1.9.2, and the applications note in Appendix A, “Host Design Considerations: NAND MMC and SD-
based Products.”
Table 5-5. Timing Constants Definitions
Min Max
Unit
N
CS
0
-
8 Clock Cycles
N
CR
0
8
8 Clock Cycles
N
RC
1
-
8 Clock Cycles
N
AC
1
See Note
8 Clock Cycles
N
WR
1
-
8 Clock Cycles
N
EC
0
-
8 Clock Cycles
N
DS
0
-
8 Clock Cycles
N
BR
0
1
8 Clock Cycles
NOTE
: min [{{(TAAC
∗
f) + (NSAC
∗
100)}
∗
1/8}, {(100ms * f) * 1/8}] where units = (8 clocks) and “f” is the clock
frequency.
5.5. SPI Electrical Interface
The SPI Mode electrical interface is identical to that of the SD Card mode.
5.6. SPI Bus Operating Conditions
Identical to SD Card mode.
5.7. Bus Timing
Identical to SD Card mode. The timing of the CS signal is the same as any other card input.
