Disk Drive Operation
5-
14 WA31273A / WA32543A / WA33203A / WA32163A / WA31083A /
more track seeks. The seek operation of this length is accomplished with a velocity control loop.
The drives ROM stores the velocity profile in look-up table.
The feed forward compensation is used while the bandwidth of the control loop is kept low.
5-4
Read and Write Operations
The following two sections describe the read channel and write channel operations.
5-4-1
The Read Channel
The drive has one read/write head for each of the data surfaces. The signal path for the read channel
starts at the read/write heads. When the magnetic flux transitions recorded on a disk pass under the
head, they generate low-amplitude, differential output voltages. The read/write head transfers these
signals to the flexible circuit’s preamplifier, which amplifies the signal.
The flexible circuit transmits the preamplified signal from the HDA to the PCBA. The PRML channel
on the PCBA shapes, filters, detects, synchronizes and decodes the data from the disk. The
Read/Write IC then sends the resynchronized data output to the SID-9501D (Disk Controller block).
The SID-9501D Disk Controller block manages the flow of data between the Data Synchronizer on the
Read/Write IC and its AT Interface Controller. It also controls data access for the external RAM
butter. The ENDEC of SSI32P4910BP decodes the 8,9 GCR format to give a serial bit stream. This
NRZ (Non Return to Zero) serial data is converted to 8-bit bytes.
The Sequencer module identifies the data as belonging to the target sector. After a full sector is read,
the SID-9501D checks to see if the firmware needs to apply an ECC algorithm to the data. The buffer
Controller section of the SID-9501D stores the data in the cache and transmits the data to the AT bus.
5-4-2
The Write Channel
The signal path for the write channel follows the reverse order of that for the read channel. The host
transmits data via the AT bus to the SID-9501D Interface Controller block. The Buffer Management
block of the SID-9501D stores the data in the cache. Because the data is transmitted to the drive at a
rate that exceeds the rate at which the drive can write data to the disk, data is stored temporarily in the
cache. Thus, the host can present data to the drive at a rate independent of the rate at which the drive
can write data to the disk.
Upon correct identification of the target address, the data is shifted to the Sequencer which generates
and appends an error correcting code. The Sequencer then converts the bytes of data to a serial bit
stream. The AT controller also generates a preamble field, inserts an address mark, and transmits the
data to the ENDEC in the R/W IC where the data is encoded into the 8,9 GCR format and
precompensates for non-linear transition shift. The amount of write current is set by 3 GPIO signals
that come from the SID-9501D integrated controller chip.
The SID-9501D switches the Preamplifier and Write Driver IC to write mode and selects a head. Once
the Preamplifier and Write Driver IC receives a write gate signal, it transmits current reversals to the
head, which writes magnetic transitions on the disk
