Samsung
Confidential
KBC3_LANLOWPWR#
soft strap read
SPI Signals
Raise at the same time as SLPS3#
MCH soft straps
CLK0_HOST_CPU
>= 1ms
Due to Pull-up to P3.3V_AUX
P5.0V / P3.3V / P1.5V
32 ~ 38 RTCCLK
0 ~ 100ns after VRM3_PWRGD Low
2 ~ 10 RTCCLK
CHECK
Px.xV_ALW
C
2
Sx Entry Ack
REV
COM-22C-015(1996.6.5) REV. 3
THIS DOCUMENT CONTAINS CONFIDENTIAL
B
S0
S3
ELECTRONICS
S5
PCI3_RST*
CHP3_SLPM*
C
0 ~ 100ns
A
1 ~ 2 RTCCLK
KBC3_RST*
CLK0_HOST_GMCH
SAMSUNG ELECTRONICS CO’S PROPERTY.
B
2
BSEL[2:0]
VCCP_PWRGD
KBC3_VRON
P3.3V_MICOM
BIOS Boot
VDC
CL0 (MCH-ICH)
CHP3_S4STATE*
Sx Entry Req
4
1 ~ 2 RTCCLK
SAMSUNG PROPRIETARY
CLK0_HOST_GMCH
BIOS Boot
CHP3_SLPS4*
CL3_RST0*
>= 0s
<= 100us
KBC3_CHKPWRSW#
0 ~ 1ms
CHP3_SUSSTAT*
>= 20ms
S5
PLT3_RST*
KBC3_RSMRST*
SMM SLP_EN Write
Due to enabled wake event, such as PWRBTN#
VRM3_CPU_PWRGD
1 ~ 2 RTCCLK
KBC3_PWRGD
DEV. STEP
3
OF
Timing Diagram, no ME
G3
VCC_CORE
1
S3
S3
LAST EDIT
KBC3_CHKPWRSW#
Toggling (Valid)
KBC3_PWRGDMCH
1
SUSPWRGD
D
S0
CHP3_PCISTP*
PART NO.
TITLE
CHP3_SLPS4*
Prepare for ME off
CHP3_SLPM*
P1.05V
>= 99ms
ADT3_SEL
P5.0V / P3.3V / P1.5V
Toggling (Valid)
VCCP_PWRGD
EXCEPT AS AUTHORIZED BY SAMSUNG.
Toggling (Valid)
CPU1_CPURST*
CLK3_PWRGD
DMI
CPU1_CPUPWRGD
CPU1_CPUPWRGD
CPU_RST_DONE/ACK
>= 1ms
PCI3_RST*
>= 5ms
P1.05V
KBC3_PWRON
KBC3_VRON
CL0 (MCH-ICH)
CHP3_PCISTP*
Raise at the same time as SLPS4#
KBC3_PWRGD
CHP3_SLPS5*
CL3_RST0*
CLK3_PWRGD
ADT3_SEL
2 ~ 3 RTCCLK
SPI Signals
KBC3_PWRGDMCH
DMI
Rev. 0.2 Phil 2006-9-21
P0.9V
CHP3_SUSSTAT*
CLK0_HOST_CPU
>= 16ms, ICH internal debounce
KBC3_RST*
5 ~ 7 RTCCLK
Px.xV_AUX
APPROVAL
P3.3V_MICOM
3
P1.25V / P2.5V
S4 / S5
SAMSUNG
S0
P1.8V / P1.2V
DRAW
KBC3_PWRON
KBC3_LANLOWPWR#
KBC3_SUSPWRON
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
SUSPWRGD
L2 / L3
VCC_CORE
VRM3_CPU_PWRGD
4
PROPRIETARY INFORMATION THAT IS
DATE
A
CPU1_CPURST*
PLT3_RST*
>= 0
MODULE CODE
2 ~ 4 RTCCLK
>= 3ms
BSEL[2:0]
CHP3_CPUSTP*
S3
1 ~ 2 RTCCLK
PAGE
D
Px.xV_ALW
VDC
CHP3_SLPS3*
CHP3_CPUSTP*
CHP3_S4STATE*
Valid
P0.9V
P1.8V / P1.2V
ZHOU JUN
GUO LEI
KEVIN LEE
3/9/2007
MP
1.0
March 9, 2007 12:03:21 PM
BA41-00727/8A
5
53
TORINO 2
MAIN
TIMING DIAGRAM
D:/users/mentor/Torino2/SR/T2_SR_0309
1 ~ 2 RTCCLK, Refer to D31:F0:A4h bits 5:3
KBC3_SUSPWRON
Px.xV_AUX
CHP3_SLPS3*
KBC3_RSMRST*
CHP3_SLPS5*
P1.25V / P2.5V