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SGH-V206 Circuit Description
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10. Camera ASIC(SSH 275)
This ASIC interfaces between CCD and LCD, and this chip compresses and expands
input pictures from CCD with JPEG format.
- CCD I/F : YUV422(16 bit) format, CIF fixed size.
System clock providing CCD module (13.5 MHz) and Dot clock providing
CCD module (13.5 MHz).
- CPU I/F : Accessible to JPEG controller, a control register including, JPEG code buffer,
and a thumbnail picture buffer.
Direct access to LCD controller by switching buses.
- LCD I/F : Support LCD controller.
Accessible by switching 2 masters of the Host CPU or ASIC picture
processing .
Output format from ASIC is RGB565.
- I2C I/F : I2C master for CCD module control equipped.
CCD module is accessible from CPU wiithout paying attention to I2C, as in the
case of a normal register write/read.
- JPEG codec : YUV422 picture data is compressed to JPEG code, and JPEG code data is
expanded to YUV422 picture data.
- Clock system : As for ASIC, 27 MHz clock input from outside is the main clock.
2-divided 13.5 MHz is used as CCD module main clock output, dot clock
output to CCD module, and ASIC inner clock
