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2. SGH-D500 Circuit Description
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1. SGH-D500 RF Circuit Description
1) RX PART
1. ANTENNA SWITCH (U100 SWICHPLEXER)
→
Switching Tx, Rx path for GSM900, DCS1800 and PCS1900 by logic controlling.
2. ANTENNA SWITCH Control Losic (U100)
→
Truth Table
VC1
VC2
VC3
Tx Mode (GSM900)
L
H
L
Tx Mode (DCS1800/1900)
L(H)
L
H
Rx Mode (GSM900)
L
L
L
Rx Mode (DCS1800)
L
L
L
Rx Mode (PCS1900)
H
L
L
3. FILTER
To convert Electromagnetic Field Wave to Acoustic Wave and then pass the specific frequency band.
- GSM FILTER (F100)
→
For filtering the frequency band between 925 and 960 MHz
- DCS FILTER (F102)
→
For filtering the frequency band between 1805 and 1880 MHz.
- PCS FILTER (F101)
→
For filtering the frequency band between 1930 and 1990 MHz.
4. VC-TCXO (U101)
This module generates the 26MHz reference clock to drive the logic and RF.
It is turned on when the supply voltage Vcc(SYN) is applied.
After buffering a reference clock of 26MHz is supplied to the other parts of the system
through the transceiver pin CLKOUT.
5. TRANSCEIVER (U102)
This chip is fully integrated GSM GPRS quad-band transceiver with transmit baluns, loop filters and most of the
passive component in it.
And also fully integrated fractional N RF synthesizer with AFC control possibility, RF VCO with integrated supply
regulator. Semi integrated reference oscillator with integrated supply regulator.
RF Receiver front-end amplifies the E-GSM900, DCS1800 and PCS1900 aerial signal, convert the chosen channel
down to a low IF of 100kHz.
In IF section, further amplifies the wanted channel output level to the desired value and rejects DC.
2) TX PART
The transmitter is fully differential using a direct up conversion architecture. It consists of a signal side band
power up mixer. Gain is controlled by 6 dB via 3-wire serial bus programing. The fully integrated VCO and power
mixer achieve LO suppression, quadrature phase error, quadrature amplitude balance and low noise floor specification.
Output matching/balun components drive a standard 50 ohms single ended load.