5-2-2. Jupiter-2 Chip
KS32C6500 internal logic generates chip select
signals for both memory chips and peripherals. To
support external access, from one to three wait
cycles can be inserted under program control during
external accesses. A chip select signal line goes
active (low) whenever its corresponding device is
accessed over the external interface. The peripheral
addresses are located in data memory.
/SRAMCS : SRAM chip select active (low)
/ ROMCS : EP-ROM chip select active (low)
D0ÐD15 : 16 bit data bus
A0ÐA17 : address bus
5-2-3. System Clock
The 30 MHz internal system clock frequency is
supplied by an external clock generator.
5-2
Samsung Electronics
Circuit Description
Figure 5-2 Hardware Interface Signals
OPERATING
PANEL
SERIAL
COMMUNICATION
HEAD
DRIVER
RTC
CRYSTAL
(32, 768KHZ)
SDIP4
TAD PART
KS32C6500
MOTOR
DRIVER
(CR, LF
MOTOR)
DATA
MEMORY
(SRAM)
PROGRAM
MEMORY
(EPROM)
DRAM.
(USER MEMORY)
GENERAL
PURPOSE I/ 0
TXD
A0~A5
D0~D15 D0~D7
CONTROL
RXD
PHINA~D
CONTROL
+24
XIN
ONLY SF3000T
XOUT
/DMS
/RD/WR
D0~D7
A0~A14
/RD
/LCAS
/RASO~
/UCAS
D0~D15
A0~A17
/A16
/PMS
/RD/WR
D0~D7
A0~A4
/RESET
/RESTO
MODEM
Содержание SF3000
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Страница 101: ...12 1 Main Circuit Diagram Samsung Electronics 12 1 12 Schematic Diagrams CPU ...
Страница 102: ...Schematic Diagrams 12 2 Samsung Electronics SCAN I O ...
Страница 103: ...Memory Motor Samsung Electronics 12 3 Schematic Diagrams ...
Страница 104: ...Schematic Diagrams 12 4 Samsung Electronics Modem ...
Страница 105: ...DSPG Samsung Electronics 12 5 Schematic Diagrams ...
Страница 106: ...Schematic Diagrams 12 6 Samsung Electronics Head Driver ...
Страница 107: ...Connector Samsung Electronics 12 7 Schematic Diagrams ...
Страница 110: ...Schematic Diagrams 12 10 Samsung Electronics 12 4 Home Circuit Diagram 5V GND5 CN1 2 CN1 3 1 2 3 4 HOME CN1 1 ...
Страница 111: ...Samsung Electronics 12 11 Schematic Diagrams 12 5 AFPS V2 1 ...
Страница 114: ... Samsung Electronics Co Ltd Jul 1998 Printed in Korea P N JB68 60988A ELECTRONICS ...