Samsung S5PC110, Руководство пользователя

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S5PC110_UM 8 TRANSPORT STREAM INTERFACE
8-13
8.1.5.5 TS_CLK Filter
When HCLK maintains the same level as TS_CLK at the rising edge during two consecutive clock cycles,
TS_CLK filter considers TS_CLK as valid.
In case TS_CLK filter is used, a half-period of the TS_CLK should have two or more periods of HCLK. The
maximum frequency of TS_CLK will change depending on whether TS_CLK passes two-stage flip-flops (noise
filter is disabled) or TS_CLK passes three-stage flip-flops (noise filter is enabled).
If HCLK with an operating frequency of 132MHz is used, the maximum frequency of TS_CLK is limited by 66MHz
(without TS_CLK filter) and 33MHz (with TS_CLK filter).
Figure 8-8
shows the block diagram of TS_CLK filter.
CK
D Q
CK
D Q
CK
D Q TS_CLK
HCLK
Noise Filter
Synchronizer
A
B
S0
Y
TS_CLK_1dff
TS_CLK_2dff TS_CLK_3dff
Figure 8-8 Block Diagram of TS_CLK Filter
8.1.5.6 Transport Stream Write
After the transport stream is received from the channel chip, it is stored in internal FIFO (32-word). The TSI sends
the transport stream to the output buffer (DRAM) depending on the selected burst length (1-/ 4-/ 8-beat). Using
word-aligned address, the TSI sends data streams to the output buffer (SDRAM). One packet size is equal to 47
words. The output buffer size should be equal to a multiple of 47 words (one packet size). If the data is written in
the output buffer, the SDRAM full interrupt is generated and the destination address is reloaded in the base
address.