Samsung S3P80C5, Руководство пользователя

Страница: 205 / 263

RESET RESET
and POWER-DOWN S3P80C5/C80C5/C80C8
8-4
HARDWARE RESET VALUES
Tables 5-1 list the reset values for CPU and system registers, peripheral control registers, and peripheral data
registers following a reset operation. The following notation is used to represent reset values:
— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
— An 'x' means that the bit value is undefined after a reset.
— A dash ('-') means that the bit is either not used or not mapped (but a 0 is read from the bit position)
Table 8-1. Set 1 Register Values After Reset
Register Name Mnemonic Address Bit Values After Reset
Dec Hex 7 6 5 4 3 2 1 0
Timer 0 counter (read-only) T0CNT 208 D0H 0 0 0 0 0 0 0 0
Timer 0 data register T0DATA 209 D1H 1 1 1 1 1 1 1 1
Timer 0 control register T0CON 210 D2H 0 0 0 0 0 0 0 0
Basic timer control register BTCON 211 D3H 0 0 0 0 0 0 0 0
Clock control register CLKCON 212 D4H 0 0 0 0 0 0 0 0
System flags register FLAGS 213 D5H
× × × × × ×
0 0
Register pointer 0 RP0 214 D6H 1 1 0 0 0 – – –
Register pointer 1 RP1 215 D7H 1 1 0 0 1 – – –
Location D8H (SPH) is not mapped.
Stack pointer (low byte) SPL 217 D9H
× × × × × × × ×
Instruction pointer (high byte) IPH 218 DAH
× × × × × × × ×
Instruction pointer (low byte) IPL 219 DBH
× × × × × × × ×
Interrupt request register (read-only) IRQ 220 DCH 0 0 0 0 0 0 0 0
Interrupt mask register IMR 221 DDH
× × × × × × × ×
System mode register SYM 222 DEH 0 – –
× × ×
0 0
Register page pointer PP 223 DFH 0 0 0 0 0 0 0 0
Port 0 data register P0 224 E0H 0 0 0 0 0 0 0 0
Port 1 data register P1 225 E1H 0 0 0 0 0 0 0 0
Port 2 data register P2 226 E2H 0 0 0 0 0 0 0 0
Location E3H–E6H is not mapped.
Port 0 pull-up enable register P0PUR 231 E7H 0 0 0 0 0 0 0 0
Port 0 control register (high byte) P0CONH 232 E8H 0 0 0 0 0 0 0 0
Port 0 control register (low byte) P0CONL 233 E9H 0 0 0 0 0 0 0 0