S3FM02G_USER'S GUIDE_REV 1.00
1 S3FM02G DESCRIPTION
1-2
1.2 S3FM02G Block Diagram
CM3
Core
Interrupts
sleep
debug
N
V
I
V
S
W
J
-
D
P
Systick
AHB-AP
In
s
t
D
a
ta
DWP
ITM
APB
I-
C
o
d
e
D
-C
o
d
e
S
-B
U
S
Cortex-M3
Cortex-M3
APB
E
T
M
T
P
I
U
INTNMI
INTISR
NMI
I/
O
c
o
n
f
G
P
IO
JTAG/SWDBG
AHB Bus Matrix
Program Flash
384KB
PF Controller
Data Flash
16KB
DF Controller
SRAM
24KB
SRAM Controller
AHB2APB
DMA
Con.
CM
IVC Controller
PLLCLK (8 ~ 75MHz)
EMCLK (4 ~ 8MHz)
IMCLK (8/16/20MHz)
ESCLK (32.768KHz)
ISCLK (32.768KHz)
I/
O
c
o
n
f
G
P
IO
PLL
IMOSC20
IMOSC16
ISOSC
IVC
WDT
12-BIT
ADC0
12-BIT
ADC0
10-BIT
ADC0
5ch
OP-AMP
ADC 0/1
Controller
I/
O
c
o
n
f
G
P
IO
OP-AMP
Controller
FRT
8-ch
Timer/Counter
8ch PWM
4ch USART
2ch SSP
2ch I2C
2ch IMC
2ch ENC
2ch CAN
4 com x 40 seg
LCD Controller
From CM
STT
Figure 1-1 Block Diagram