Samsung
Confidential
1
SAMSUNG ELECTRONICS CO’S PROPERTY.
100 MHz
0
0
1
B
3
3
0
D
SAMSUNG
Merom 667MHz
D
0
0
400 MHz
EXCEPT AS AUTHORIZED BY SAMSUNG.
FSB
Silego : SLG84610
FSA, FSB, FSC of Clock chip are low thershold inputs
1
Pt decoupling CAPS close to Clock Chip power pin
0
1
B
Vih_fs_min = 0.7V
1
RSVD
266 MHz
Vil_fs_max - 0.35V
BSEL0
2
A
Celeron 533MHz
FSA
1
CPU
1
0
4
1
Compatible Components
SAMSUNG PROPRIETARY
4
1
BSEL2
133 MHz
BSEL1
0
1
PROPRIETARY INFORMATION THAT IS
FSC
1
0
333 MHz
0
C
166 MHz
0
C
HOST CLK
Place all te serias termination resistor as close as Clock Chip as possible
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
A
Route all CLK1 signal as different pair rule
1
Merom 800MHz
2
THIS DOCUMENT CONTAINS CONFIDENTIAL
0
200 MHz
1
ELECTRONICS
1
C576
13-B3
R544
1%
100nF
33
R41
49.9
R64
33
100nF
C577
29-C4
49.9
R542
1%
27-C4
20-C3
C590
0.022nF
2.2K
13-B3
19-A4
49.9
P3.3V
R60
1%
R546
29-C4
100nF
C575
49.9
R551
1%
33
R42
33
R43
C586
10000nF
6.3V
X1
X2
3
1%
R550
49.9
SRCCLKT2
SRCCLKT3
24
20
SRCCLKT4
SRCCLKT5
18
16
SRCCLKT6
12
SRCCLKT7
50
VDDA
VDDCPU
56
4
VDD_48
VDD_ATIG
39
VDD_REF
1
VDD_SRC1
44
28
VDD_SRC2
VDD_SRC3
23
VDD_SRC4
14
VTTPWRGD*_PD
8
2
22
GND_SRC4
15
IREF
48
RESET_IN*
60
SMBCLK
9
SMBDAT
10
46
SRCCLKC0
31
SRCCLKC1
SRCCLKC2
27
25
SRCCLKC3
SRCCLKC4
21
19
SRCCLKC5
SRCCLKC6
17
13
SRCCLKC7
SRCCLKT0
47
SRCCLKT1
30
26
53
51
CPUC2
CPUT0
58
54
CPUT1
CPUT2
52
CPU_STOP*
59
FSLA_REF0
63
62
FSLB_REF1
FSLC_REF2
61
49
GNDA
GND_48
7
GND_ATIG
38
55
GND_CPU
GND_REF
64
GND_SRC1
45
GND_SRC2
29
GND_SRC3
5
48MHZ_0
48MHZ_1
6
42
ATIGCLKC0
40
ATIGCLKC1
ATIGCLKC2
36
ATIGCLKC3
34
ATIGCLKT0
43
ATIGCLKT1
41
ATIGCLKT2
37
ATIGCLKT3
35
11
CLKREQA*
CLKREQB*
32
33
CLKREQC*
57
CPUC0
CPUC1
20-D2
U8
ICS951461
34-C3 42-C4
100nF
C571
35-D4
15-B4
13-B3
R38
33
R65
0
6.3V
10000nF
C574
9-C4
9-C4
15-B4
33
R44
4700nF
C587
6.3V
B506
BLM18PG181SN1
1%
R548
49.9
33
R34
nostuff
9-C4
1M
R568
1%
R541
49.9
27-C3
29-C2
20-C3
20-A4
17-B4
17-B2
1%
R540
49.9
1%
R567
49.9
33
R33
R36
33
nostuff
9-D4
19-D4
C588
100nF
10V
1%
R562
49.9
R40
33
9-B2
R57
33
R45
33
20-C3
20-A4
27-C4
C572
10nF
0
R28
R62
2.2K
P3.3V
27-C4
C53
BLM18PG181SN1
B505
1
2
0.022nF
Y501
14.31818MHz
B504
33
R63
17-B2
29-C2
27-C4
17-B4
20-A4
20-C3
19-D4
BLM18PG181SN1
R66
13-B3
49.9
R563
1%
33
R564
49.9
1%
33
R39
R61
2.2K
100nF
C573
R58
49.9
R545
1%
33
29-C4
C54
0.022nF
P3.3V
R67
33
R35
475
49.9
R547
1%
10V
1%
R37
33
100nF
C589
9-D4
35-D4
33
R59
49.9
R543
1%
15-B4
R549
1%
CLK3_USB48
MINIPCIE3_CLKREQ#
EXP3_CLKREQ#
49.9
CLK0_HCLK1#
CLK1_PCIEICH#
CLK1_NBSRC#
CLK1_PCIELOM#
CLK1_EXPCARD#
CLK1_PCIELOM
CLK0_HCLK0#
CLK0_HCLK0
CLK1_PCIEICH
CLK1_NBSRC
CLK1_PCIERCLK
CLK1_MINIPCIEA#
CLK1_MINIPCIEA
CLK1_PCIERCLK#
CLK1_EXPCARD
CLK3_ICH14
CPU1_BSEL1
CLK3_NB14M
CLK0_HCLK1
CPU1_BSEL0
CPU1_BSEL2
SMB3_CLK
SMB3_DATA
CLK3_PWRGD#
CHP3_CPUSTP#
ITP3_DBRESET#
