
6. Schematic Diagram
6.13. INTERFACE/SATA BLOCK
O_UART3_NRTS
I_UART3_NCTS
I2C0_DDC
DELETE LAYER 2,3,4,5,6 COP P ER FOR IMP EDANCE
1
0
K
O
H
M
D3.3V_P W
CE3.3V
D1.1V_P W
D3.3V_P W
D3.3V_B
D3.3V_P W
D3.3V_T
D3.3V_P W
1
/1
6
W
2
.2
K
O
H
M
4.7KOHM
D3.3V_P W
IP OD_VD_S W
IP OD_RS T
I_EXTINT1
US B_RES ET
I_EXTINT2
GP IO7
GP IO4
GP IO5
I_EXTINT1
GP IO0
OTN_INT
CKEIN_REQ
FRONT_INTB
IP OD_RS T
S P I_NS S O
BOOT_MODE
IP OD_DET
IP OD_VD_S W
S P I_NS S I
DRM_WP
DRM_S DA
UART2_RX
IP OD_S CL
CEC_TX
DRM_S CL
UART1_TX
DRM_WP
UART2_TX
IP OD_S DA
CEC_RX
UART1_RX
VARI_B
VARI_A
S P I_S IO
S P I_MIO
S P I_CLK
UART1_TX
UART1_RX
DRM_S DA
DRM_S CL
DRM_WP
DDC_S DA
DDC_S CL
S ATA0_TX-
S ATA0_RX-
S
S
S
S ATA0_RX-
S ATA0_TX-
S
S DP 1004
IC29
A24
A25
A26
A27
AH1
AH2
AH3
AH4
AJ 11
AJ 12
AJ 13
AJ 5
AJ 6
AJ 7
AK1
AK11
AK12
AK13
AK2
AK3
AK4
AK5
AK6
AK7
AL11
AL13
AL14
AL3
AL4
AL5
AL6
AL7
AM11
AM12
AM13
AM14
AM3
AM4
AM5
AM6
AM7
AM8
B25
B26
B27
C23
C24
C25
C26
C27
D22
D23
D24
D25
D26
D27
4.7KOHM
R258
4.7KOHM
R259
4.7KOHM
R257
4.7KOHM
R256
R215
33OHM
R252
33OHM
R279
33OHM
R278
33OHM
R277
DGND
2
.7
K
O
H
M
1
/1
6
W
R
8
2
5
33OHM
R231
33OHM
R230
33OHM
R229
33OHM
R228
33OHM
R227
33OHM
R226
33OHM
R251
33OHM
R250
33OHM
R240
33OHM
R241
33OHM
R242
33OHM
R246
33OHM
R801
33OHM
R802
33OHM
R803
1
/1
6
W
2
.7
K
O
H
M
R
9
4
3
1
/1
6
W
2
.7
K
O
H
M
R
1
4
1
N
C
R
2
0
6
D3.3V_P W
NC
R244
33OHM
R237
33OHM
R236
33OHM
R235
33OHM
R234
33OHM
R233
33OHM
R232
N
C
R
2
0
7
1/16W
2.7KOHM
R
1
4
2
DGND
2KOHM
O
R
1
2KOHM
O
R
2
NC
OR4
S
T
K
7
0
0
2
O
T
Q
1
S
T
K
7
0
0
2
O
T
Q
2
NC
OR3
33OHM
R225
33OHM
R224
33OHM
R223
33OHM
R222
33OHM
R220
DGND
O
P
T
IO
N
1
2
V
L
O
P
IV
A
1
6
G
0
5
V
T
9
5
O
P
T
IO
N
L
O
P
IV
A
1
6
G
0
5
1
2
V
V
T
9
6
U
A
R
T
1
_
R
X
U
A
R
T
1
_
T
X
1
/1
6
W
2
.2
K
O
H
M
R
2
9
9
1
/1
6
W
R
3
0
0
2
.2
K
O
H
M
R
3
0
1
D
W
P
_
T
D
W
P
_
B
D
S
C
_
T
DGND
1
0
0
N
F
1
6
V
C
8
0
2
D
S
C
_
B
D
S
D
_
T
D
S
D
_
B
AT24C256C-S S HL-T
IC28
1
2
3
4
5
6
7
8
DGND
CE3.3V
DGND_B
DGND_T
DGND
1
6
V
1
0
0
N
F
C
9
7
1
1
0
0
N
F
1
6
V
C
9
7
2
1
0
0
N
F
1
6
V
C
9
7
3
1
0
0
N
F
1
6
V
C
9
7
4
1
0
0
N
F
1
6
V
C
9
7
5
1
0
0
N
F
1
6
V
C
9
7
6
1
0
0
N
F
1
6
V
C
9
7
7
DGND
S DP 1004
IC29
H2
H3
H4
J 1
J 2
J 3
K1
K2
K3
K4
L1
L3
L4
M1
M2
M3
M4
M5
N1
N2
N3
N4
N5
P 2
P 3
P 4
R1
R2
R3
R4
R5
T1
T2
T3
T4
T5
1
0
0
N
F
1
6
V
C
9
7
8
P CIE_CM
S ATA_CP
S ATA_CM
P CIE_CP
TP 92
3KOHM
1/10W
R989
1/10W
3KOHM
R990
TP 91
DGND
KT-S A07A-15AKB7-U
OP TION
CN95
1
2
3
4
5
6
7
DGND
DGND
CN99
1
2
3
4
1
/1
6
W
R
9
9
9
*
0
.0
1
O
H
M
B
D
7
7
* 0
.0
1
O
H
M
B
D
7
8
16V
10NF
C979
10NF
16V
C981
16V
10NF
C980
16V
10NF
C982
b_RMI_S IO7
b_RMI_S IO6
b_RMI_S IO5
b_RMI_S IO4
b_RMI_S IO3
b_RMI_S IO2
b_RMI_S IO1
b_RMI_S IO0
o_RMI_RS CK
o_RMI_READY
i_RMI_WVALID
i_RMI_S CK
i_RMI_CEn
b_GP IO0
b_GP IO1
b_GP IO2
b_GP IO3
b_GP IO4
b_GP IO5
b_GP IO6
b_GP IO7
i_EXTINT0
i_EXTINT1
i_EXTINT2
o_S DCARD_CLK
b_S DCARD_CMD
b_S DCARD_DATA0
b_S DCARD_DATA1
b_S DCARD_DATA2
b_S DCARD_DATA3
b_S DCARD_DATA4
b_S DCARD_DATA5
b_S DCARD_DATA6
b_S DCARD_DATA7
i_S DCARD_DET_N
i_S DCARD_WP
i_UART0_nCTS
o_UART0_nRTS
i_UART0_RX
o_UART0_TX
i_UART1_RX
o_UART1_TX
i_UART2_RX
o_UART2_TX
b_I2C0_CLK
b_I2C0_DATA
b_I2C1_CLK
b_I2C1_DATA
b_I2C2_CLK
b_I2C2_DATA
b_I2C3_CLK
b_I2C3_DATA
o_S P I_CLK
o_S P I_MIO
o_S P I_NS S I
i_S P I_S IO
S
D
G
S
D
G
S DA
VS S
WP
VCC
S CL
A2
A1
A0
i_AY_S ATA1_REFCLKP
i_AY_S ATA1_REFCLKM
i_AY_S ATA0_REFCLKP
i_AY_S ATA0_REFCLKM
i_AY_S ATA1_REFRES
i_AY_S ATA0_REFRES
o_AY_S ATA1_ATES T
o_AY_S ATA0_ATES T
o_AY_S ATA1_TXCLK_DIVN
o_AY_S ATA1_TXCLK_DIVP
i_AY_S ATA1_RXP
i_AY_S ATA1_RXN
o_AY_S ATA1_TXN
o_AY_S ATA1_TXP
o_AY_S ATA0_TXCLK_DIVN
o_AY_S ATA0_TXCLK_DIVP
i_AY_S ATA0_RXP
i_AY_S ATA0_RXN
o_AY_S ATA0_TXN
o_AY_S ATA0_TXP
i_AY_S ATA1_VS S 2
i_AY_S ATA1_VS S 1
p_AY_S ATA1_VS S A2
p_AY_S ATA1_VS S A1
i_AY_S ATA0_VS S 2
i_AY_S ATA0_VS S 1
p_AY_S ATA0_VS S A2
p_AY_S ATA0_VS S A1
p_AY_S ATA1_VDDT
p_AY_S ATA1_VDDHA
p_AY_S ATA1_VDDA
p_AY_S ATA1_VDD
p_AY_S ATA0_VDDT
p_AY_S ATA0_VDDHA
p_AY_S ATA0_VDDA
p_AY_S ATA0_VDD
O_UART3_NRTS
I_UART3_NCTS
I2C0_DDC
DELETE LAYER 2,3,4,5,6 COP P ER FOR IMP EDANCE
1
0
K
O
H
M
D
3.3V_P W
CE3.3V
D1.1V_P W
D3.3V_P W
D3.3V_P W
D3.3V_P W
1
/1
6
W
2
.2
K
O
H
M
4.7KOHM
D
3.3V_P W
S
DP 1004
4.7KOHM
4.7KOHM
4.7KOHM
4.7KOHM
33OHM
33OHM
33OHM
33OHM
DGND
2
.7
K
O
H
M
1
/1
6
W
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
1
/1
6
W
2
.7
K
O
H
M
1
/1
6
W
2
.7
K
O
H
M
N
C
D3.3V_P W
NC
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
N
C
1/16W
2.7KOHM
DGND
2KOHM
2KOHM
NC
S
T
K
7
0
0
2
S
T
K
7
0
0
2
NC
33OHM
33OHM
33OHM
33OHM
33OHM
DGND
O
P
T
IO
N
1
2
V
L
O
P
IV
A
1
6
G
0
5
O
P
T
IO
N
L
O
P
IV
A
1
6
G
0
5
1
2
V
1
/1
6
W
2
.2
K
O
H
M
1
/1
6
W
2
.2
K
O
H
M
DGND
1
0
0
N
F
1
6
V
AT24C256C-S S HL-T
DGND
CE3.3V
DGND
1
6
V
1
0
0
N
F
1
0
0
N
F
1
6
V
1
0
0
N
F
1
6
V
1
0
0
N
F
1
6
V
1
0
0
N
F
1
6
V
1
0
0
N
F
1
6
V
1
0
0
N
F
1
6
V
DGND
S DP 1004
1
0
0
N
F
1
6
V
3KOHM
1/10W
1/10W
3KOHM
DGND
KT-S A07A-15AKB7-U
OP TION
DGND
DGND
1
/1
6
W
*
0
.0
1
O
H
M
* 0
.0
1
O
H
M
16V
10NF
10NF16V
16V
10NF
16V
10NF
D
3.3V_B
D3.3V_T
I
C29
R258
R259
R257
R256
R215
R252
R279
R278
R277
R
8
2
5
R231
R230
R229
R228
R227
R226
R251
R250
R240
R241
R242
R246
R801
R802
R803
R
9
4
3
R
1
4
1
R
2
0
6
R244
R237
R236
R235
R234
R233
R232
R
2
0
7
R
1
4
2
O
R
1
O
R
2
OR4
O
T
Q
1
O
T
Q
2
OR3
R225
R224
R223
R222
R220
V
T
9
5
V
T
9
6
U
A
R
T
1
_
R
X
U
A
R
T
1
_
T
X
R
2
9
9
R
3
0
0
R
3
0
1
D
W
P
_
T
D
W
P
_
B
D
S
C
_
T
C
8
0
2
D
S
C
_
B
D
S
D
_
T
D
S
D
_
B
IC28
DGND_B
DGND_T
C
9
7
1
C
9
7
2
C
9
7
3
C
9
7
4
C
9
7
5
C
9
7
6
C
9
7
7
IC29
C
9
7
8
P CIE_CM
S ATA_CP
S ATA_CM
P CIE_CP
TP 92
R989
R990
TP 91
CN95
CN99
R
9
9
9
B
D
7
7
B
D
7
8
C979
C981
C980
C982
IP OD_VD_S W
IP OD_RS T
I_EXTINT1
US B_RES ET
I_EXTINT2
GP IO7
GP IO4
GP IO5
I_EXTINT1
GP IO0
OTN_INT
CKEIN_REQ
FRONT_INTB
IP OD_RS T
S P I_NS S O
BOOT_MODE
IP OD_DET
IP OD_VD_S W
S P I_NS S I
DRM_WP
DRM_S DA
UART2_RX
IP OD_S CL
CEC_TX
DRM_S CL
UART1_TX
DRM_WP
UART2_TX
IP OD_S DA
CEC_RX
UART1_RX
VARI_B
VARI_A
S P I_S IO
S P I_MIO
S P I_CLK
UART1_TX
UART1_RX
DRM_S DA
DRM_S CL
DRM_WP
DDC_S DA
DDC_S CL
S ATA0_TX-
S ATA0_RX-
S
S
S
S ATA0_RX-
S ATA0_TX-
S
A24
A25
A26
A27
AH1
AH2
AH3
AH4
AJ 11
AJ 12
AJ 13
AJ 5
AJ 6
AJ 7
AK1
AK11
AK12
AK13
AK2
AK3
AK4
AK5
AK6
AK7
AL11
AL13
AL14
AL3
AL4
AL5
AL6
AL7
AM11
AM12
AM13
AM14
AM3
AM4
AM5
AM6
AM7
AM8
B25
B26
B27
C23
C24
C25
C26
C27
D22
D23
D24
D25
D26
D27
1
2
3
4
5
6
7
8
H2
H3
H4
J 1
J 2
J 3
K1
K2
K3
K4
L1
L3
L4
M1
M2
M3
M4
M5
N1
N2
N3
N4
N5
P 2
P 3
P 4
R1
R2
R3
R4
R5
T1
T2
T3
T4
T5
1
2
3
4
5
6
7
1
2
3
4
b_RMI_S IO7
b_RMI_S IO6
b_RMI_S IO5
b_RMI_S IO4
b_RMI_S IO3
b_RMI_S IO2
b_RMI_S IO1
b_RMI_S IO0
o_RMI_RS CK
o_RMI_READY
i_RMI_WVALID
i_RMI_S CK
i_RMI_CEn
b_GP IO0
b_GP IO1
b_GP IO2
b_GP IO3
b_GP IO4
b_GP IO5
b_GP IO6
b_GP IO7
i_EXTINT0
i_EXTINT1
i_EXTINT2
o_S DCARD_CLK
b_S DCARD_CMD
b_S DCARD_DATA0
b_S DCARD_DATA1
b_S DCARD_DATA2
b_S DCARD_DATA3
b_S DCARD_DATA4
b_S DCARD_DATA5
b_S DCARD_DATA6
b_S DCARD_DATA7
i_S DCARD_DET_N
i_S DCARD_WP
i_UART0_nCTS
o_UART0_nRTS
i_UART0_RX
o_UART0_TX
i_UART1_RX
o_UART1_TX
i_UART2_RX
o_UART2_TX
b_I2C0_CLK
b_I2C0_DATA
b_I2C1_CLK
b_I2C1_DATA
b_I2C2_CLK
b_I2C2_DATA
b_I2C3_CLK
b_I2C3_DATA
o_S P I_CLK
o_S P I_MIO
o_S P I_NS S I
i_S P I_S IO
S
D
G
S
D
G
S DAVS S
WP
VCC
S CLA2
A1
A0
i_AY_S ATA1_REFCLKP
i_AY_S ATA1_REFCLKM
i_AY_S ATA0_REFCLKP
i_AY_S ATA0_REFCLKM
i_AY_S ATA1_REFRES
i_AY_S ATA0_REFRES
o_AY_S ATA1_ATES T
o_AY_S ATA0_ATES T
o_AY_S ATA1_TXCLK_DIVN
o_AY_S ATA1_TXCLK_DIVP
i_AY_S ATA1_RXP
i_AY_S ATA1_RXN
o_AY_S ATA1_TXN
o_AY_S ATA1_TXP
o_AY_S ATA0_TXCLK_DIVN
o_AY_S ATA0_TXCLK_DIVP
i_AY_S ATA0_RXP
i_AY_S ATA0_RXN
o_AY_S ATA0_TXN
o_AY_S ATA0_TXP
i_AY_S ATA1_VS S 2
i_AY_S ATA1_VS S 1
p_AY_S ATA1_VS S A2
p_AY_S ATA1_VS S A1
i_AY_S ATA0_VS S 2
i_AY_S ATA0_VS S 1
p_AY_S ATA0_VS S A2
p_AY_S ATA0_VS S A1
p_AY_S ATA1_VDDT
p_AY_S ATA1_VDDHA
p_AY_S ATA1_VDDA
p_AY_S ATA1_VDD
p_AY_S ATA0_VDDT
p_AY_S ATA0_VDDHA
p_AY_S ATA0_VDDA
p_AY_S ATA0_VDD
P
OWER
6-16
Copyright© 1995-2011 SAMSUNG. All rights reserved.
Содержание HT-D4500
Страница 49: ...5 PCB Diagram 5 2 2 Test Point Wave Form TP1 Copyright 1995 2011 SAMSUNG All rights reserved 5 4 ...
Страница 55: ...5 PCB Diagram 5 5 1 Test Point Wave Form TP4 TP5 TP6 TP7 Copyright 1995 2011 SAMSUNG All rights reserved 5 10 ...
Страница 61: ...6 Schematic Diagram 6 2 1 Test Point Wave Form TP1 Copyright 1995 2011 SAMSUNG All rights reserved 6 3 ...
Страница 72: ...6 Schematic Diagram 6 11 1 Test Point Wave Form TP2 TP3 6 14 Copyright 1995 2011 SAMSUNG All rights reserved ...