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Confidential and proprietary-the contents in this service guide subject to change without prior notice.
8-29
C
2
8
5
L
2
1
7
R
2
1
0
R205
C
2
9
4
C
2
7
9
C
2
3
4
C
2
7
3
C
2
9
6
OSC200
2
4
3
1
C263
R214
C
2
8
8
TP209
R
2
0
9
TP225
VDD_CBUCK_1P35
L
2
2
9
L
2
2
2
VDD_LDO3P3_B
C
2
7
8
VDD_LDO3P3_B
TP219
C
2
3
0
C270
VDD_BTWIFI_1P8
C
2
5
1
C
2
3
3
TP218
VDD_LNLDO_1P2
TP216
TP208
VDD_CLDO_1P2
TP210
L
2
3
8
BTLDO2P5
C
2
9
3
VDD_LDO3P3_B
C
2
8
6
L
2
2
8
C
2
2
9
C260
TP224
R
2
1
2
C
2
8
4
C
2
4
7
C
2
4
3
TP223
W
R
F
_
S
Y
N
T
H
_
V
B
A
T
_
V
D
D
3
P
3
V
6
WRF_RFIN_2G_core1
V7
V8
WRF_RFOUT_2G_core1
W
R
F
_
P
A
2
G
_
V
B
A
T
_
V
D
D
3
P
3
_
c
o
re
1
V
9
WRF_RFIN_5G_core0
V1
W
R
F
_
P
A
5
G
_
V
B
A
T
_
V
D
D
3
P
3
_
c
o
re
1
V
1
0
V11
WRF_RFOUT_5G_core1
WRF_RFIN_5G_core1
V12
W
R
F
_
L
N
A
_
5
G
_
G
N
D
1
P
2
_
c
o
re
0
V
2
W
R
F
_
R
X
5
G
_
G
N
D
1
P
2
_
c
o
re
0
V
3
W
R
F
_
B
U
C
K
_
G
N
D
1
P
5
_
c
o
re
0
V
4
W
R
F
_
C
P
_
G
N
D
1
P
2
V
5
W
R
F
_
P
A
5
G
_
V
B
A
T
_
G
N
D
3
P
3
_
c
o
re
0
U
2
WRF_TSSI_A_core0
U3
U
4
W
R
F
_
B
U
C
K
_
V
D
D
1
P
5
_
c
o
re
0
W
R
F
_
P
F
D
_
G
N
D
1
P
2
U
5
W
R
F
_
V
C
O
_
G
N
D
1
P
2
U
6
W
R
F
_
L
N
A
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2
G
_
G
N
D
1
P
2
_
c
o
re
1
U
7
W
R
F
_
P
A
2
G
_
V
B
A
T
_
G
N
D
3
P
3
_
c
o
re
1
U
8
W
R
F
_
P
A
2
G
_
V
B
A
T
_
G
N
D
3
P
3
_
c
o
re
1
U
9
W
R
F
_
M
M
D
_
G
N
D
1
P
2
T
6
W
R
F
_
R
X
2
G
_
G
N
D
1
P
2
_
c
o
re
1
T
7
T
8
W
R
F
_
T
X
_
G
N
D
1
P
2
_
c
o
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1
W
R
F
_
P
A
D
R
V
_
V
B
A
T
_
V
D
D
3
P
3
_
c
o
re
1
T
9
WRF_RFOUT_5G_core0
U1
W
R
F
_
P
A
5
G
_
V
B
A
T
_
G
N
D
3
P
3
_
c
o
re
1
U
1
0
W
R
F
_
P
A
5
G
_
V
B
A
T
_
G
N
D
3
P
3
_
c
o
re
1
U
1
1
W
R
F
_
L
N
A
_
5
G
_
G
N
D
1
P
2
_
c
o
re
1
U
1
2
W
R
F
_
P
A
5
G
_
V
B
A
T
_
V
D
D
3
P
3
_
c
o
re
0
T
1
W
R
F
_
P
A
D
R
V
_
V
B
A
T
_
G
N
D
3
P
3
_
c
o
re
1
T
1
0
T11
WRF_TSSI_A_core1
W
R
F
_
R
X
5
G
_
G
N
D
1
P
2
_
c
o
re
1
T
1
2
W
R
F
_
P
A
5
G
_
V
B
A
T
_
G
N
D
3
P
3
_
c
o
re
0
T
2
W
R
F
_
P
A
D
R
V
_
V
B
A
T
_
G
N
D
3
P
3
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c
o
re
0
T
3
W
R
F
_
P
F
D
_
V
D
D
1
P
2
T
4
W
R
F
_
M
M
D
_
V
D
D
1
P
2
T
5
W
R
F
_
P
A
2
G
_
V
B
A
T
_
G
N
D
3
P
3
_
c
o
re
0
R
2
W
R
F
_
P
A
D
R
V
_
V
B
A
T
_
V
D
D
3
P
3
_
c
o
re
0
R
3
R4
WRF_GPIO_OUT_core0
W
R
F
_
L
O
G
E
N
G
_
G
N
D
1
P
2
R
5
W
R
F
_
L
O
G
E
N
_
G
N
D
1
P
2
R
6
RF_SW_CTRL_0
R7
W
R
F
_
A
F
E
_
G
N
D
1
P
2
_
c
o
re
1
R
8
WRF_GPIO_OUT_core1
R9
W
R
F
_
T
X
_
G
N
D
1
P
2
_
c
o
re
0
P
3
W
R
F
_
A
F
E
_
G
N
D
1
P
2
_
c
o
re
0
P
4
P5
RF_SW_CTRL_6
RF_SW_CTRL_5
P7
RF_SW_CTRL_2
P9
W
R
F
_
P
A
2
G
_
V
B
A
T
_
V
D
D
3
P
3
_
c
o
re
0
R
1
W
R
F
_
B
U
C
K
_
V
D
D
1
P
5
_
c
o
re
1
R
1
1
W
R
F
_
B
U
C
K
_
G
N
D
1
P
5
_
c
o
re
1
R
1
2
W
R
F
_
R
X
2
G
_
G
N
D
1
P
2
_
c
o
re
0
N
3
RF_SW_CTRL_4
N5
N7
RF_SW_CTRL_3
RF_SW_CTRL_1
N8
WRF_RFOUT_2G_core0
P1
W
R
F
_
X
T
A
L
_
V
D
D
1
P
5
P
1
1
WRF_XTAL_IN
P12
W
R
F
_
P
A
2
G
_
V
B
A
T
_
G
N
D
3
P
3
_
c
o
re
0
P
2
BT_PCM_CLK
M6
V
D
D
C
M
7
M8
RF_SW_CTRL_7
WRF_RFIN_2G_core0
N1
W
R
F
_
X
T
A
L
_
V
D
D
1
P
2
N
1
0
W
R
F
_
X
T
A
L
_
G
N
D
1
P
2
N
1
1
WRF_XTAL_OUT
N12
W
R
F
_
L
N
A
_
2
G
_
G
N
D
1
P
2
_
c
o
re
0
N
2
RF_SW_CTRL_15
L8
RF_SW_CTRL_11
L9
M1
BT_PAVDD2P5
RF_SW_CTRL_14
M10
RF_SW_CTRL_10
M12
B
T
_
IF
V
S
S
M
3
V
S
S
C
M
4
V
D
D
C
M
5
V
D
D
C
L
1
0
V
S
S
C
L
1
1
L
2
B
T
_
P
A
V
S
S
B
T
_
P
L
L
V
S
S
L
3
BT_DEV_WAKE
L4
BT_UART_CTS_L
L5
BT_I2S_WS
L6
V
S
S
C
L
7
RF_SW_CTRL_8
K12
BT_PLLVDD1P2
K2
K3
BT_IFVDD1P2
BT_GPIO_4
K4
BT_UART_RTS_L
K5
BT_PCM_SYNC
K6
BT_VDDO
K7
BT_RF
L1
BT_HOST_WAKE
J3
BT_PCM_IN
J4
J5
BT_UART_TXD
BT_I2S_CLK
J6
V
D
D
C
J
8
RF_SW_CTRL_12
J9
BT_LNAVDD1P2
K1
RF_SW_CTRL_13
K10
BT_PCM_OUT
H4
BT_UART_RXD
H5
H
7
A
V
D
D
_
B
B
P
L
L
GPIO_4
H9
BT_VCOVDD1P2
J1
RF_SW_CTRL_9
J11
V
D
D
C
J
1
2
B
T
_
V
C
O
V
S
S
J
2
A
V
S
S
_
B
B
P
L
L
G
7
V
S
S
C
G
8
G9
GPIO_3
FM_RFIN
H1
V
D
D
IO
_
R
F
H
1
1
GPIO_10
H12
F
M
_
L
N
A
V
S
S
H
2
V
D
D
C
H
3
V
D
D
C
G
1
0
GPIO_0
G11
G
1
2
V
S
S
C
F
M
_
V
C
O
V
S
S
G
2
F
M
_
P
L
L
V
S
S
G
3
V
S
S
C
G
4
BT_I2S_DI
G5
BT_I2S_DO
G6
FM_PLLVDD1P2
F3
CLK_REQ
F4
F5
BT_USB_DP
LPO_IN
F6
GPIO_8
F7
GPIO_6
F8
GPIO_5
F9
FM_LNAVCOVDD1P2
G1
GPIO_7
E7
V
D
D
IO
_
S
D
E
8
E
9
V
D
D
C
FM_AOUT2
F1
GPIO_1
F10
GPIO_2
F11
V
O
U
T
_
3
P
3
F
1
2
F
M
_
A
U
D
IO
V
S
S
F
2
FM_AOUT1
E1
V
D
D
IO
E
1
0
E
1
1
V
O
U
T
_
L
D
O
3
P
3
_
B
L
D
O
_
V
D
D
B
A
T
5
V
E
1
2
FM_AUDIOVDD1p2
E2
V
D
D
C
E
4
BT_USB_DN
E5
GPIO_9
E6
V
O
U
T
_
L
N
L
D
O
D
1
1
V
O
U
T
_
B
T
L
D
O
2
P
5
D
1
2
D
3
V
S
S
C
V
D
D
C
D
4
PCIE_CLKREQ_L
D5
V
S
S
C
D
6
RREFHSIC
D7
JTAG_SEL
D9
PCIE_TESTP
C3
PCIE_PERST_L
C4
C5
PCIE_PME_L
H
S
IC
_
D
V
D
D
1
2
C
6
H
S
IC
_
A
V
D
D
1
2
C
7
SDIO_DATA_3
C8
SDIO_DATA_1
C9
BT_REG_ON
D10
V
D
D
C
B
7
SDIO_DATA_2
B8
B9
SDIO_DATA_0
PCIE_RDP
C1
V
S
S
C
C
1
0
V
O
U
T
_
C
L
D
O
C
1
1
L
D
O
_
V
D
D
1
P
5
C
1
2
PCIE_TESTN
C2
P
M
U
_
A
V
S
S
B
1
0
S
R
_
V
D
D
B
A
T
A
5
V
B
1
1
B
1
2
S
R
_
V
D
D
B
A
T
P
5
V
P
C
IE
_
R
X
T
X
_
A
V
D
D
1
P
2
B
2
P
C
IE
_
P
L
L
_
A
V
D
D
1
P
2
B
3
P
C
IE
_
R
X
T
X
_
A
V
S
S
B
4
P
C
IE
_
P
L
L
_
A
V
S
S
B
5
H
S
IC
_
A
G
N
D
1
2
B
6
PCIE_TDN
A3
PCIE_REFCLKP
A4
A5
PCIE_REFCLKN
HSIC_DATA
A6
HSIC_STROBE
A7
SDIO_CLK
A8
SDIO_CMD
A9
PCIE_RDN
B1
U206
1
MARK
MARK
2
WL_REG_ON
A10
S
R
_
V
L
X
A
1
1
S
R
_
P
V
S
S
A
1
2
PCIE_TDP
A2
L
2
2
4
C265
C
2
4
8
C
2
3
7
TP220
C
2
8
9
C
2
4
5
C259
TP212
TP215
VDD_LDO3P3
C
2
4
9
C
2
7
7
R
2
0
7
C
2
3
1
C261
C
2
8
3
VDD_CBUCK_1P35
C
2
3
5
C256
L231
TP222
C266
TP221
C
2
4
6
VDD_CBUCK_1P35
BTLDO2P5
R
2
1
3
C
2
9
5
L
2
2
7
C
2
3
6
VDD_BTWIFI_1P8
C267
VDD_LDO3P3
VDD_LDO3P3
C
2
3
2
VDD_LNLDO_1P2
TP214
C264
VDD_BTWIFI_1P8
C255
L
2
2
3
VDD_LDO3P3_B
C271
C
2
8
1
C
2
3
8
TP217
VBAT_4354K
VBAT_4354K
C269
L230
TP211
C
2
8
2
L
2
2
5
R
2
1
1
TP213
C268
C253
R203
C262
C
2
8
7
C
2
4
1
C252
C
2
3
9
VDD_LDO3P3_B
R206
C
2
8
0
VDD_CLDO_1P2
R
2
0
4
VDD_CLDO_1P2
C
2
7
2
L
2
2
6
WLAN_HOST_WAKE
BT_TX
BT_WIFI_CLK32K
SW_BT_TX
SW_WL_5G_LNA_EN_1
SW_WL_5G_TX_1
SW_WL_5G_RX_1
SW_WL_2G_TX_1
WL_TX_G_CORE1_CAP
WL_RX_G_CORE1_ETR
WL_TX_A_CORE1_CAP
WL_RX_A_CORE1_ETR
WL_TX_A_CORE0_CAP
WL_RX_A_CORE0_ETR
WL_TX_G_CORE0_CAP
WL_RX_G_CORE0_ETR
BT_PCM_CLK
BT_PCM_IN
BT_PCM_OUT
BT_WAKE
BT_HOST_WAKE
WLAN_SDIO_D(3)
WLAN_SDIO_D(0)
WLAN_SDIO_CLK
BT_UART_RTS
BT_UART_TXD
BT_UART_CTS
BT_UART_RXD
BT_EN
WLAN_EN
BT_PCM_SYNC
WLAN_SDIO_CMD
WLAN_SDIO_D(2)
WLAN_SDIO_D(1)
SW_WL_5G_TX_0
SW_WL_2G_RX_0
SW_WL_5G_RX_0
SW_WL_5G_LNA_EN_0
SW_WL_2G_LNA_EN_1
SW_WL_2G_RX_1
SW_WL_2G_TX_0
SW_WL_2G_LNA_EN_0
(I2C_5_SCL)
(I2C_2_SDA)
(I2C_4_SDA)
(I2C_6_SCL)
(I2C_5_SDA)
(I2C_2_SCL)
(I2C_3_SCL)
(I2C_3_SDA)
(I2C_7_SDA)
(I2C_7_SCL)
(I2C_4_SCL)
(I2C_6_SDA)
C4100
R4087
Y7
XUTXD_3
Y1
XUSB30OVERCUR_U2
Y2
XUSB30VBUSCTRL_U3
Y3
XUFSNRESET
Y33
XJTMS
Y34
XJDBGSEL
Y4
XUHOSTOVERCUR
Y5
XUHOSTPWREN
Y6
XURXD_3
W3
XUSB31OVERCUR_U3
W33
XJTCK
W34
XJTRSTN
W4
XUSB31VBUSCTRL_U2
W5
XUSB31OVERCUR_U2
W6
XI2C8SDA_HS
W7
XUTXD_2
W8
XI2C9SCL_HS
V3
XI2C1SDA
V4
XUSB31VBUSCTRL_U3
V5
XI2C8SCL_HS
V6
XI2C1SCL
V7
XI2C10SDA_HS
V8
XI2C0SDA
W1
XUSB30OVERCUR_U3
W2
XUSB30VBUSCTRL_U2
U4
XURTSN_2
XI2C10SCL_HS
U5
U6
XI2C9SDA_HS
U7
XUTXD_0
U8
XPWMTOUT_1
V
2
1
X
T
S
T
E
S
T
_
O
U
T
0
V
2
3
X
T
S
T
E
S
T
_
O
U
T
4
V
2
4
X
T
S
E
X
T
_
R
E
S
4
T5
XPWMTOUT_0
T6
XURXD_1
T7
XURTSN_0
T8
XI2C0SCL
U
1
2
X
T
S
E
X
T
_
R
E
S
1
U
2
0
X
T
S
E
X
T
_
R
E
S
0
U3
XURTSN_1
R6
XI2S2SCLK
R7
XURXD_0
R8
XUCTSN_2
T
1
P
O
P
_
V
R
E
F
C
A
_
E
2
T
1
2
X
T
S
T
E
S
T
_
O
U
T
1
T3
XPWMTOUT_3
T32
XDRAM1VREF2
T4
XPWMTOUT_2
P
1
X
U
S
B
3
R
X
0
M
_
1
P
2
P
O
P
_
Z
Q
_
E
2
P
4
X
U
H
O
S
T
D
P
P5
XI2S2SDO
P7
XUCTSN_0
P8
XURXD_2
R2
XI2S1LRCK
P
O
P
_
V
R
E
F
D
Q
_
E
2
R
3
2
R5
XI2S2CDCLK
M7
XI2S2LRCK
M8
XI2S1SDI
N
1
X
U
S
B
3
R
X
0
P
_
1
N
3
X
U
H
O
S
T
V
B
U
S
N
4
X
U
H
O
S
T
D
M
N
5
X
U
H
O
S
T
R
E
X
T
N7
XUTXD_1
N8
XUCTSN_1
L3
XUSB3REFPADCLKP_1
L5
XUSB3RESREF_1
L6
XSPIMISO_0
L7
XSPICLK_1
L8
XI2S1SCLK
M
2
P
O
P
_
Z
Q
1
_
E
2
M5
XUHOSTANALOGTEST
M6
XSPIMOSI_0
J8
XI2S1SDO
K
1
X
U
S
B
3
T
X
0
P
_
1
K
3
X
U
S
B
3
D
P
0
_
1
K6
XSPICSN_1
K7
XSPIMISO_1
K8
XI2S1CDCLK
L
1
X
U
S
B
3
T
X
0
M
_
1
L2
XUSB3REFPADCLKM_1
H
4
X
U
S
B
3
V
B
U
S
0
_
1
H6
XSPICLK_0
H7
XADC0AIN_0
H8
XI2S2SDI
J
3
X
U
S
B
3
D
M
0
_
1
J
5
X
U
S
B
3
ID
0
_
1
J6
XSPIMOSI_1
J7
XSPICSN_0
G2
XUSB3REFPADCLKP_0
G3
XUSB3RESREF_0
G6
XADC0AIN_2
G7
XADC0AIN_5
G8
XADC0AIN_1
G9
XADC0AIN_4
H
1
X
U
S
B
3
R
X
0
M
_
0
H33
XDRAM1VREF0
F7
XADC0AIN_3
F
9
X
G
P
IO
1
5
G
1
X
U
S
B
3
R
X
0
P
_
0
G10
XADC0AIN_7
G11
XADC0AIN_8
G12
XADC0AIN_9
G
1
3
X
T
S
T
E
S
T
_
O
U
T
2
G
1
4
X
T
S
E
X
T
_
R
E
S
2
F
1
1
X
E
IN
T
_
0
F
1
4
X
C
L
K
O
U
T
F
1
5
X
E
IN
T
_
6
F
1
8
X
T
S
E
X
T
_
R
E
S
3
F
1
9
X
T
S
T
E
S
T
_
O
U
T
3
F2
XUSB3REFPADCLKM_0
F33
XDRAM1ZQ
F6
XADC0AIN_6
E
1
9
X
N
W
R
E
S
E
T
E
3
X
U
S
B
3
D
P
0
_
0
E
4
X
U
S
B
3
V
B
U
S
0
_
0
X
U
S
B
3
ID
0
_
0
E
5
E
7
X
G
P
IO
8
E
8
X
G
P
IO
9
E
9
X
G
P
IO
1
0
F
1
0
X
G
P
IO
1
2
D
3
X
U
S
B
3
D
M
0
_
0
D
4
X
A
U
D
I2
S
0
C
D
C
L
K
D
6
X
G
P
IO
3
D
7
X
G
P
IO
6
D
9
X
G
P
IO
1
4
E
1
X
U
S
B
3
T
X
0
M
_
0
E
1
0
X
G
P
IO
1
1
E
1
4
X
N
R
E
S
E
T
D20
XDRAM0VREF0
D
2
1
X
O
M
_
0
D
2
2
X
E
IN
T
_
4
D
2
4
X
E
IN
T
_
2
D
2
5
X
E
IN
T
_
1
0
D
2
6
X
E
IN
T
_
1
1
D27
XDRAM0VREF2
D
2
8
X
E
IN
T
_
1
6
C
6
X
G
P
IO
2
C
7
X
G
P
IO
5
C
8
X
G
P
IO
7
D
1
X
U
S
B
3
T
X
0
P
_
0
D
1
0
X
G
P
IO
1
3
D
1
3
X
P
W
R
R
G
T
O
N
D18
XDRAM0ZQ
D
1
9
X
O
M
_
5
C
2
6
X
R
T
C
C
L
K
O
C
2
8
X
E
IN
T
_
2
5
C
2
9
X
E
IN
T
_
2
7
C
3
X
A
U
D
I2
S
0
L
R
C
K
C
3
0
X
E
IN
T
_
3
0
C
3
1
X
E
IN
T
_
2
9
C
4
X
A
U
D
I2
S
0
S
C
L
K
C
5
X
A
U
D
I2
S
0
S
D
O
_
0
C
1
8
X
P
S
H
O
L
D
C
1
9
X
O
M
_
6
C
2
0
P
O
P
_
V
R
E
F
D
Q
_
E
1
C
2
1
X
E
IN
T
_
3
1
C
2
2
X
E
IN
T
_
2
1
C
2
3
X
E
IN
T
_
1
7
C
2
4
X
E
IN
T
_
1
8
C
2
5
X
E
IN
T
_
2
0
B
6
X
G
P
IO
0
X
G
P
IO
1
B
7
C10
XHSICSTROBE1
C11
XHSICDATA1
C
1
2
X
E
IN
T
_
3
C
1
3
X
O
M
_
3
C
1
5
X
O
M
_
1
X
N
R
S
T
O
U
T
C
1
7
B
2
0
X
O
M
_
2
B
2
2
X
E
IN
T
_
1
9
B
2
6
X
E
IN
T
_
1
4
B
2
7
X
E
IN
T
_
2
8
B
2
8
X
E
IN
T
_
2
3
B
3
0
X
E
IN
T
_
2
4
B
3
1
X
E
IN
T
_
2
2
B
5
X
A
U
D
I2
S
0
S
D
O
_
1
A
V
1
6
P
O
P
_
V
R
E
F
C
A
_
E
1
AV27
XADC1AIN_1
AV30
XV1FRM
B
1
2
X
X
T
I
B
1
5
X
E
IN
T
_
5
B
1
6
X
R
T
C
X
T
I
B
1
7
X
O
M
_
4
B
1
8
X
E
IN
T
_
1
5
A
U
1
3
X
M
IP
I1
V
R
E
G
_
0
P
4
V
AU19
XHDMIREXT
AU27
XADC1AIN_0
AU28
XADC1AIN_3
AU29
XADC1AIN_2
AU30
XV1VSYNC_LDI
A
U
3
1
X
G
P
IO
1
7
A
V
1
2
P
O
P
_
Z
Q
_
E
1
AT3
XMIPI0VREG_0P4V
A
T
3
1
X
G
P
IO
1
6
AT4
XMIPI0MDP3
AT5
XMIPI0MDP2
AT6
XMIPI0MDPCLK
AT7
XMIPI0MDP1
AT8
XMIPI0MDP0
A
U
1
2
P
O
P
_
Z
Q
1
_
E
1
AT19
XHDMITX2P
AT20
XHDMIXTI
AT21
XDPRBIAS
AT22
XDPAUXP
AT23
XDPTX0P
AT24
XDPTX1P
AT25
XDPTX2P
AT26
XDPTX3P
A
T
1
1
X
M
IP
I1
M
D
P
2
A
T
1
2
X
M
IP
I1
M
D
P
C
L
K
A
T
1
3
X
M
IP
I1
M
D
P
1
A
T
1
4
X
M
IP
I1
M
D
P
0
AT16
XHDMITXCP
AT17
XHDMITX0P
AT18
XHDMITX1P
AR28
XISPGP4
AR29
XISPI2C2SDA
AR30
XISPI2C0SCL
AR4
XMIPI0MDN3
AR5
XMIPI0MDN2
AR6
XMIPI0MDNCLK
AR7
XMIPI0MDN1
AR8
XMIPI0MDN0
A
T
1
0
X
M
IP
I1
M
D
P
3
AR19
XHDMITX2N
AR20
XHDMIXTO
AR22
XDPAUXN
AR23
XDPTX0N
AR24
XDPTX1N
AR25
XDPTX2N
AR26
XDPTX3N
AR27
XISPGP5
A
R
1
0
X
M
IP
I1
M
D
N
3
A
R
1
1
X
M
IP
I1
M
D
N
2
A
R
1
2
X
M
IP
I1
M
D
N
C
L
K
A
R
1
3
X
M
IP
I1
M
D
N
1
A
R
1
4
X
M
IP
I1
M
D
N
0
AR16
XHDMITXCN
AR17
XHDMITX0N
AR18
XHDMITX1N
AP28
XISPGP1
AP29
XISPGP0
AP30
XISPI2C0SDA
AP4
XMIPI0SDP3
AP5
XMIPI0SDP2
AP6
XMIPI0SDPCLK
XMIPI0SDP1
AP7
AP8
XMIPI0SDP0
AP19
XISPSPI0CSN
AP20
XISPGP6
AP21
XISPSPI1MISO
AP22
XISPSPI1CSN
XISPI2C2SCL
AP23
AP24
XISPI2C1SDA
AP25
XISPGP7
AP27
XISPGP2
XMIPI0SDN0
AN9
XMMC2DATA_2
AP1
XUFSXTI
A
P
1
0
X
M
IP
I1
S
D
P
3
A
P
1
1
X
M
IP
I1
S
D
P
2
A
P
1
2
X
M
IP
I1
S
D
P
C
L
K
A
P
1
3
X
M
IP
I1
S
D
P
1
A
P
1
4
X
M
IP
I1
S
D
P
0
XISPGP8
AN25
XISPSPI0CLK
AN27
XISPGP3
AN28
XISPI2C1SCL
AN4
XMIPI0SDN3
AN5
XMIPI0SDN2
AN6
XMIPI0SDNCLK
AN7
XMIPI0SDN1
AN8
A
N
1
4
X
M
IP
I1
S
D
N
0
A
N
1
6
X
C
I1
R
G
B
_
4
A
N
1
7
X
C
I1
R
G
B
_
0
AN19
XISPGP9
AN20
XISPSPI1MOSI
AN21
XISPSPI0MISO
AN22
XISPSPI1CLK
AN23
XISPSPI0MOSI
AN24
AM6
XMMC2BIUVR
AM7
XMMC2CLK
AM9
XMMC0CMD
AN1
XUFSXTO
A
N
1
0
X
M
IP
I1
S
D
N
3
A
N
1
1
X
M
IP
I1
S
D
N
2
A
N
1
2
X
M
IP
I1
S
D
N
C
L
K
A
N
1
3
X
M
IP
I1
S
D
N
1
A
M
1
3
X
C
I1
V
S
Y
N
C
A
M
1
4
X
C
I1
R
G
B
_
9
A
M
1
5
X
C
I1
R
G
B
_
1
0
A
M
1
6
X
C
I1
R
G
B
_
3
A
M
1
7
X
C
I1
R
G
B
_
7
AM3
XUFSTXDP1
AM4
XUFSTXDN1
AM5
XMMC2DATA_0
A
L
1
7
X
C
I1
P
C
L
K
AL3
XUFSTXDP0
XUFSTXDN0
AL4
AL5
XMMC2DATA_3
AL6
XMMC2CDN
AM10
XMMC2DATA_1
AM11
XMMC2CMD
A
M
1
2
X
C
I1
H
S
Y
N
C
AK9
XMMC0RDQS
AL10
XMMC0CLK
XMMC0DATA_3
AL11
A
L
1
2
X
C
I1
M
C
L
K
A
L
1
3
X
C
I1
R
G
B
_
1
3
A
L
1
4
X
C
I1
R
G
B
_
5
A
L
1
5
X
C
I1
R
G
B
_
6
A
L
1
6
X
C
I1
R
G
B
_
1
A
K
1
4
X
C
I1
R
G
B
_
1
2
A
K
1
5
X
C
I1
R
G
B
_
8
A
K
1
6
X
C
I1
R
G
B
_
2
AK3
XUFSREFCLK_OUT
AK4
XUFSREFCLK
AK5
XMMC2WP
AK6
XMMC0CDN
AK7
XMMC0DATA_6
AJ3
XUFSRXDP0
AJ4
XUFSRXDN0
AJ5
XMMC1DATA_2
AJ6
XMMC1DATA_3
AJ8
XMMC0DATA_2
AJ9
XMMC0DATA_7
AK10
XMMC1CDN
X
C
I1
R
G
B
_
1
1
A
K
1
3
AH3
XUFSRXDP1
AH4
XUFSRXDN1
AH5
XMMC1DATA_7
AH6
XMMC1INTN
AH8
XMMC1DATA_1
A
H
9
X
S
R
A
M
C
S
N
_
0
AJ10
XMMC1DATA_0
A
J
1
1
X
S
R
A
M
C
S
N
_
2
A
G
5
X
S
R
A
M
B
E
N
_
1
A
G
6
X
S
R
A
M
W
A
IT
N
A
G
7
X
S
R
A
M
B
E
N
_
0
A
G
8
X
S
R
A
M
D
A
T
A
_
1
A
G
9
X
S
R
A
M
D
A
T
A
_
0
A
H
1
0
X
S
R
A
M
C
S
N
_
3
A
H
1
1
X
S
R
A
M
C
S
N
_
1
AH2
XUFSREXT
A
F
8
X
S
R
A
M
D
A
T
A
_
4
A
F
9
X
S
R
A
M
D
A
T
A
_
6
AG1
XMMC0DATA_1
A
G
1
0
X
S
R
A
M
D
A
T
A
_
R
D
N
A
G
1
1
X
S
R
A
M
W
E
N
AG2
XMMC0DATA_0
AG3
XMMC0DATA_4
A
G
4
X
S
R
A
M
O
E
N
A
E
8
X
S
R
A
M
D
A
T
A
_
1
1
A
E
9
X
S
R
A
M
D
A
T
A
_
1
3
A
F
1
0
X
S
R
A
M
D
A
T
A
_
3
AF3
XMMC0DATA_5
A
F
4
X
S
R
A
M
D
A
T
A
_
2
A
F
5
X
S
R
A
M
D
A
T
A
_
5
A
F
6
X
S
R
A
M
D
A
T
A
_
7
A
F
7
X
S
R
A
M
D
A
T
A
_
8
A
D
7
X
S
R
A
M
D
A
T
A
_
1
4
A
D
8
X
S
R
A
M
F
R
N
B
_
2
A
D
9
X
S
R
A
M
F
C
L
E
A
E
1
0
X
S
R
A
M
D
A
T
A
_
1
0
AE3
XMMC0RESETOUT
A
E
5
X
S
R
A
M
F
A
L
E
A
E
6
X
S
R
A
M
D
A
T
A
_
1
2
X
S
R
A
M
D
A
T
A
_
9
A
E
7
A
C
7
X
S
R
A
M
A
D
D
R
_
5
A
C
8
X
S
R
A
M
F
R
N
B
_
1
AD1
XMMC1CMD
A
D
1
0
X
S
R
A
M
D
A
T
A
_
1
5
AD2
XMMC1CLK
AD3
XMMC1RDQS
A
D
5
X
S
R
A
M
F
R
N
B
_
0
A
D
6
X
S
R
A
M
A
D
D
R
_
1
AC1
XMMC1DATA_5
AC2
XMMC1DATA_4
AC3
XMMC1BEPW
A
C
3
3
X
O
M
C
C
I
AC34
XJTDI
A
C
4
X
S
R
A
M
A
D
D
R
_
3
A
C
5
X
S
R
A
M
F
R
N
B
_
3
A
C
6
X
S
R
A
M
A
D
D
R
_
0
AB2
XMMC1DATA_6
AB3
XMMC1WP
AB33
XJTDO
A
B
4
X
S
R
A
M
A
D
D
R
_
8
A
B
5
X
S
R
A
M
A
D
D
R
_
1
1
A
B
6
X
S
R
A
M
A
D
D
R
_
4
A
B
7
X
S
R
A
M
A
D
D
R
_
7
A
B
8
X
S
R
A
M
A
D
D
R
_
2
AA1
XEFFSOURCE_0
A
A
2
X
S
R
A
M
A
D
D
R
_
6
A
A
3
X
S
R
A
M
A
D
D
R
_
1
0
A
A
4
X
S
R
A
M
A
D
D
R
_
1
5
X
S
R
A
M
A
D
D
R
_
1
3
A
A
5
A
A
6
X
S
R
A
M
A
D
D
R
_
1
4
A
A
7
X
S
R
A
M
A
D
D
R
_
1
2
A
A
8
X
S
R
A
M
A
D
D
R
_
9
A
2
1
X
E
IN
T
_
9
A
2
3
X
E
IN
T
_
8
A
2
5
X
E
IN
T
_
1
2
A
2
8
X
E
IN
T
_
1
3
A
2
9
X
E
IN
T
_
2
6
A
4
X
A
U
D
I2
S
0
S
D
I
A
6
X
A
U
D
I2
S
0
S
D
O
_
2
A
8
X
G
P
IO
4
NC
1
NC
2
A
1
2
X
X
T
O
X
E
IN
T
_
1
A
1
3
A
1
6
X
R
T
C
X
T
O
A
1
7
X
E
IN
T
_
7
UCP4001-1
R4109
Содержание Galaxy Tab S SM-T805
Страница 184: ...www s manuals com ...