Circuit Operating Descriptions
Samsung Electronics
13-13
• Write to Buffer
To program the flash device, a Write to Buffer command sequence is initiated.
A variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device.
First, the Write to Buffer Setup command is issued along with the Block.
At this point, the eXtended Status Register information is loaded and XSR.7 reverts to “buffer available” status.
If XSR.7 = 0, the write buffer is not available. To retry, continue monitoring XSR.7 by issuing
the Write to Buffer setup command with the Block Address until XSR.7 = 1.
When XSR.7 transitions to a “1,” the buffer is ready for loading.
Next, a word/byte count is given to the part with the Block Address.
On the next write, a device start address is given along with the write buffer data.
Subsequent writes provide additional device addresses and data, depending on the count.
All subsequent addresses must lie within the start address plus the count.
Internally, this device programs many flash cells in parallel. Because of this parallel programming, maximum
programming performance and lower power are obtained by aligning the start address at
the beginning of a write buffer boundary (i.e., A[4:0] of the start address = 0).
After the final buffer data is given, a Write Confirm command is issued.
This initiates the WSM (Write State Machine) to begin copying the buffer data to the flash array.
If a command other than Write Confirm is written to the device, an “Invalid Command/Sequence” error will
be generated and SR.5 and SR.4 will be set. For additional buffer writes, issue another Write to Buffer Setup
command and check XSR.7.
Содержание DCB-P850Z
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