A–26
System Address Space
PCI Configuration Space
1.9 PCI Configuration Space
The PCI configuration space is located in the range 87.0000.0000 to 87.1FFF.FFFF.
Software is advised to clear PYXIS_CTRL<FILL_ERR_EN> when probing for PCI
devices by way of configuration space read transactions. This will prevent the 21174
from generating an ECC error if no device responds to the configuration cycle (and
random data is picked up on the PCI bus).
A read or write transaction to this space causes a configuration read or write cycle on
the PCI. There are two classes of targets that are selected, based on the value of the
CFG register.
•
Type 0 — These are targets on the primary 64-bit PCI bus. These targets are
selected by making CFG<1:0> = 0.
•
Type 1 — These are targets on the secondary 32-bit PCI bus (that is, behind a
PCI-to-PCI bridge). These targets are selected by making CFG<1:0> = 1.
Note:
CFG<1:0> = 10 or 11 are reserved (by the PCI specification).
Software must program the CFG register before running a configuration cycle.
Sparse address decoding is used. Signals addr_h<6:3> are used to generate both the
length of the PCI transaction in bytes and the byte enable bits. Signals ad<1:0> are
obtained from CFG<1:0>. Signals addr_h<28:7> correspond to ad<23:2> and pro-
vide the configuration command information (such as which device to select). The
high-order ad<31:24> are always zero.
Figure 1–14 depicts PCI configuration space (sparse). Figure 1–15 shows PCI con-
figuration space (dense).
