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advances in semiconductor technology that allowed engineers to squeeze more bits into each cell. Capacities ballooned
from megabytes (MBs) to gigabytes (GBs) as manufacturers were able to produce the same NAND bit capacity with
less capital investment. A self-reinforcing cycle of increasing demand and decreasing pricing helped manufacturers to
continue to meet industry needs without increasing supply costs – benefiting both consumers and device makers.
Limitations of MLC NAND
Of course, adding more bits to each cell makes it more difficult to distinguish between states, reducing reliability,
endurance, and performance. Indeed, determining whether a container is either full or empty (SLC) is much simpler than
determining whether it is one quarter full, one half full, three-quarters full, or entirely full (MLC). This is why it can take up
to 4 times as long to write and up to 2.5 times as long to read 3-bit MLC NAND than its SLC predecessor.
Another side effect of storing more bits per cell is an increase in the rate at which the NAND cells degrade. The state of a NAND
cell is determined by the number of electrons present on the floating gate. The Oxide layers that trap electrons on the floating
gate wear out with every program and erase operation. As they wear out, electrons become trapped, which affects the overall
electrical properties of the cell and, consequentially, subsequent program and erase operations. With the oxide weakened,
charges sometimes leak from the floating gate. While this is not a huge problem with SLC NAND because there are only two
states to distinguish between, it can be a huge problem for 3-bit MLC NAND because there are 8 states to distinguish and very
little room for differentiation – just a few electrons can make the difference between one state or another. Compounding matters
is the fact that the oxide layer gets smaller with each advance in process geometry – as we shrink the size of the cell, the oxide
becomes thinner. A thinner oxide layer will wear out faster, meaning the cell will have a lower lifespan.
MLC NAND Today
Manufacturers have made massive strides in managing the limitations of NAND technology. Sophisticated “bin sorting”
algorithms allow 1
st
-tier manufacturers like Samsung to select only the highest-quality NAND chips for use in SSD devices.
Advanced wear-leveling code ensures that NAND cells wear out evenly (to prevent early drive failure and maintain consistent
performance), while garbage collection algorithms preemptively prepare fresh storage space (to improve write performance).
Improved Error-Correcting Code (ECC) is able to detect and recover from errors at the bit level caused by the natural wear
out of individual NAND cells. Supporting all of these maintenance features is over-provisioning, which ensures that the SSD
controller always has swap space available to accomplish its tasks. As a precautionary measure, some vendors choose to
pre-set a certain amount of mandatory over-provisioning at the factory, and there is always the option to manually set aside
additional space for even further-improved performance (e.g. under demanding workloads).
SLC 2-bit MLC 3-bit MLC
Price/GB
$$$$$ $$ $
External Storage
USB Flash Drive*
Memory card*
Mid 90’s ~
4MB ~
2MB ~
Mid 2000s ~
1GB ~
1GB ~
’09 ~
2GB ~
?
Digital Devices
Digital Camera
MP3 Player
Mid 90’s ~
4MB ~
16MB ~
Mid 2000’s
128MB ~
512MB ~
’11 ~
2GB ~
Client SSD (2.5”)
’06 ~
32GB ~
’08 ~
64GB ~
’12 ~
120GB ~
Enterprise SSD
’08 ~
50GB ~
’12 ~
128GB
’13 ~
?
* Less than 5% of Memory Cards and USB Flash Drives use SLC Memory as of 2012
Cost vs. Capacity
SLC 2-bit MLC 3-bit MLC
Bits per Cell
1 2 3
Performance
★★★★ ★★★ ★★
Endurance
★★★★ ★★★ ★★
ECC complexity
★★ ★★★ ★★★★
* Today’s SSD controllers are capable of minimizing the risks associated with 2-bit MLC and 3-bit MLC NAND through techniques like advanced Error Correcting Code (ECC).
NAND Characteristics