MXS System Description and Installation Manual
UM06945
© Sagetech Avionics 2022 Proprietary Confidential
Page 51 of 56
2
Rx Oscillator
Locked
The MXS reports a PLL Lock to software
when the Rx Oscillator is locked on
frequency.
Test is part of the Continuous BIT suite of tests.
XPDR Fail Flag is set in the ACK message to the Host.
Attempt a Power cycle. The
unit is damaged if the failure
persists
1
Tx Oscillator
Locked
The MXS reports a PLL Lock to software
when the Quadrature Modulator’s
(ADRF6750) PLL is locked on entry into
operational mode. The locked bit is cleared
after losing lock for a period greater than
300 microseconds
Test is part of the Continuous BIT suite of tests.
XPDR Fail Flag is set in the ACK message to the Host.
Attempt a Power cycle. The
unit is damaged if the failure
persists
0
Mutual
Suppression Valid
When the Mutual suppression output bus
is either stuck in a low or high state this bit
will flag a fail.
If there is a failure that results in the Suppression
output signal being tied to ground or Active High state,
then this bit will fail.
Attempt a Power cycle. The
unit is damaged if the failure
persists
BIT2
7
(msb)
Temperature In
Range
Internal temp monitored twice per second;
if >110°C, all transmissions are disabled
until monitor indicates unit has cool down
(<110°C)
Test is part of the Continuous BIT suite of tests.
XPDR Fail Flag is set in the ACK message to the Host.
Putting the unit in standby
mode or powering off (i.e.,
cutoff power or ground pin
42 for MX Power control) will
speed up the cooling
process.
Provide unit additional
cooling such as air flow or
improved heat sinking.
6
Squitter Monitor
Valid
This test checks software scheduled
Squitters against the Squitters sent out in
the FPGA. This failure is flagged if the
squitter count does not match. This test
also checks to ensure that the CRC of the
transmitted ADS-B message matches the
CRC that was measure via the transmit
monitor.
Test is part of the Continuous BIT suite of tests.
XPDR Fail Flag is set in the ACK message to the Host.
Attempt a Power cycle. The
unit is damaged if the failure
persists
5
Transmit Rate In
Range
Monitors The transmission duty cycle of
the MXS to ensure that an unsafe limit will
never be reached that could result in HW
damage.
Transmissions are dropped to avoid damage to MXS
transmitter hardware. Test is part of the Continuous
BIT suite of tests. XPDR Fail Flag is set in the ACK
message to the Host.
Determine and eliminate the
source of over-interrogation
of the MXS. Power Cycle to
clear BIT.
4
System Latency In
Range
Checks for average event duration time
and average loop duration time; events
have a limit of 2ms, loops have a limit of
5ms.
Test is part of the Continuous BIT suite of tests.
XPDR Fail Flag is set in the ACK message to the Host.
Attempt a Power cycle. The
unit is damaged if the failure
persists
