S.M.S.L DO100, Руководство пользователя

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DO100
DPLL
BRIGHTNESS
bl1-5
USB MODE
DPLL 1~9, the lower the value, the smaller the clock jitter .
This DPLL setting is a unique function of ESS series products. It can adjust the bandwidth
of the DPLL digital phase-locked loop circuit inside the chip, so that the chip can
achieve a balance between anti-clock jitter and input tolerance.
Effect:
When the clock stability of the input signal is good, this value can be reduced,
so that the clock performance of the system is better;
When the clock stability of the input signal is not good, the sound may be
interrupted. Increasing this value can avoid the occurrence of audio
interruption! Especially when using TV as the signal source.
UAC1
(
USB1.1 description: when USB1.1 is selected, the WIN system is free of drive,
and supports sampling rate 44.1-96kHz, 24bit ）
UAC2
(select USB2.0, WIN system needs to install driver, support DSD)