S.M.S.L C2OO, Руководство пользователя

Страница: 18 / 27

DPLL
BRIGHTNESS (DISPLAY BRIGHTNESS SETTING)
bL1-8 (Brightness Level 1~8, The Smaller The Value, The Lower The Brightness.)
USB MODE （USB Input）
DPLL 1~9, the lower the value, the smaller the clock jitter .
This DPLL setting is a unique function of ESS series products. It can adjust the bandwidth
of the DPLL digital phase-locked loop circuit inside the chip, so that the chip can
achieve a balance between anti-clock jitter and input tolerance.
Effect:
When the clock stability of the input signal is good, this value can be reduced,
so that the clock performance of the system is better;
When the clock stability of the input signal is not good, the sound may be
interrupted. Increasing this value can avoid the occurrence of audio
interruption! Especially when using TV as the signal source.
C2OO
U1.0 MODE, U1.1 MODE
U2.0
(USB2.0 needs to install the driver when connecting to the WIN system,
and supports high-standard sampling rate)
"MM64#EFWJDFTDBOCFDPOOFDUFEXJUIPVUESJWFS
*UDBOTVQQPSUUIFDPOOFDUJPOPGWBSJPVTHBNFDPOTPMFTTVDIBT
9#091414BOETPPO
64#POMZTVQQPSUTVQUPCJUL)[