RTD Embedded Technologies, Inc.
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15
LAN25215HR/LAN35215HR User’s Manual
5
Functional Description
Block Diagram
The Figure below shows the functional block diagram of the LAN25215/35215. The various parts of the block diagram are discussed in the
following sections.
Figure 7: LAN25215/35215 Block Diagram
PCIe Switch
The LAN25215/35215 provides a PCI Express packet switch to repopulate the lane that it uses. The uplink for the switch is attached to the host
through the PCIe/104 bus. A downlink is attached to each of the Ethernet controllers. Then another downlink is fed back to the PCIe/104 bus,
and provides connectivity to additional in card in the stack from the LAN25215/35215. This allows the PCIe/104 system to grow beyond the
maximum number of PCIe x1 links that can be provided by the host. If all of the peripherals in the system provide repopulation, a very large
number of peripherals can be used.
Fiber Ethernet Connection
5.3.1
I
NTEL
WG82574IT
G
IGABIT
E
THERNET
C
ONTROLLER
The LAN25215/35215
features two Intel’s WG82574IT Gigabit Ethernet controller
used to interface with fiber Ethernet connections. The
WG82574IT is an industrial temperature rated Gigabit Ethernet controller which features 9KB Jumbo Frame Support, 40KB packet buffer size
and IPv4/6 support.
5.3.2
C
ORTINA
(I
NTEL
)
LXT973
E
THERNET
PHY
T
RANSCEIVER
The LAN25215/35215 uses two 100Mb/s Ethernet PHY Transceiver to convert twisted-pair from the Ethernet controller to fiber connection.
5.3.3
F
IBER
E
THERNET
T
RANSCEIVER
The fiber connectors on the LAN25215/35215 are fiber transceivers. The transmitter transmits using a 1300 nm surface emitting InGaAsP LED
and the receiver receives using an InGaAs PIN photodiode.
Before installing a fiber into the connector, remove the protection plug from the connector.
82574
Gig-E
Controller
PC
Ie
Bu
s
PCIe x1
PCIe Switch
82574
Gig-E
Controller
100 Mb/s
Fiber
Transceiver
PCIe x1
Link/Speed/
Activity LED
Link/Speed/
Activity LED
Ethernet
PHY
Transceiver
100 Mb/s
Fiber
Transceiver
Ethernet
PHY
Transceiver
PCIe x1