rtd DM6210, Руководство пользователя

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6-4
Basic Programming For Interrupt Handling
• What Is an Interrupt?
An interrupt is an event that causes the processor in your computer to temporarily halt its current process and
execute another routine. Upon completion of the new routine, control is returned to the original routine at the
point where its execution was interrupted.
Interrupts are very handy for dealing with asynchronous events (events that occur at less than regular inter-
vals). Keyboard activity is a good example; your computer cannot predict when you might press a key and it
would be a waste of processor time for it to do nothing while waiting for a keystroke to occur. Thus, the interrupt
scheme is used and the processor proceeds with other tasks. Then, when a keystroke does occur, the keyboard
‘interrupts’ the processor, and the processor gets the keyboard data, places it in memory, and then returns to what
it was doing before it was interrupted. Other common devices that use interrupts are modems, disk drives, and
mice.
Your DM6210 board can interrupt the processor when a variety of conditions are met, such as timer
countdown finished, end-of-convert, and external clock. By using these interrupts, you can write software that
effectively deals with real world events.
• Interrupt Request Lines
To allow different peripheral devices to generate interrupts on the same computer, the AT bus has 16 differ-
ent interrupt request (IRQ) lines. A transition from low to high on one of these lines generates an interrupt request
which is handled by one of the AT’s two interrupt control chips. One chip handles IRQ0 through IRQ7 and the
other chip handles IRQ8 through IRQ15. The controller which handles IRQ8-IRQ15 is chained to the first
controller through the IRQ2 line. When an IRQ line is brought high, the interrupt controllers check to see if
interrupts are to be acknowledged from that IRQ and, if another interrupt is already in progress, they decide if the
new request should supersede the one in progress or if it has to wait until the one in progress is done. This
prioritizing allows an interrupt to be interrupted if the second request has a higher priority. The priority level is
determined by the number of the IRQ. Because of the configuration of the two controllers, with one chained to the
other through IRQ2, the priority scheme is a little unusual. IRQ0 has the highest priority, IRQ1 is second-highest,
then priority jumps to IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, and IRQ15, and then following
IRQ15, it jumps back to IRQ3, IRQ4, IRQ5, IRQ6, and finally, the lowest priority, IRQ7. This sequence makes
sense if you consider that the controller that handles IRQ8-IRQ15 is routed through IRQ2.
• 8259 Programmable Interrupt Controllers
The chips responsible for handling interrupt requests in the PC are the 8259 Programmable Interrupt Control-
lers. The 8259 that handles IRQ0-IRQ7 is referred to as 8259A, and the 8259 that handles IRQ8-IRQ15 is referred
to as 8259B. To use interrupts, you need to know how to read and set the 8259 interrupt mask registers (IMR) and
how to send the end-of-interrupt (EOI) command to the 8259s.
• Interrupt Mask Registers (IMR)
Each bit in the interrupt mask register (IMR) contains the mask status of an IRQ line; in 8259A, bit 0 is for
IRQ0, bit 1 is for IRQ1, and so on, while in 8259B, bit 0 is for IRQ8, bit 1 is for IRQ9, and so on. If a bit is set
(equal to 1), then the corresponding IRQ is masked and it will not generate an interrupt. If a bit is clear (equal to
0), then the corresponding IRQ is unmasked and can generate interrupts. The IMR for IRQ0-IRQ7 is programmed
through port 21H, and the IMR for IRQ8-IRQ15 is programmed through port A1H.
,54 ,54 ,54 ,54 ,54 ,54 ,54 ,54
,54 ,54 ,54 ,54 ,54 ,54 ,54 ,54
I/O Port 21H
I/O Port A1H
For all bits:
0 = IRQ unmasked (enabled)
1 = IRQ masked (disabled)