rtd DM34216HR, Руководство пользователя

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57 DM34216HR
User’s Manual
BDM-610010056 Rev A
o
’1’ = Pseudo -Differential
B[11]: Reserved
B[10]: Index: When enabled, a high input on the Index input clears the counter
o
’0’ = Index Inputs Disabled
o
’1’ = Index Input Enabled
B[9]: Hold: When enabled, the encoder continues counting in the background, but the INCENC_VALUE register remains constant.
o
’0’ = INCENC_VALUE registers are not held
o
’1’ = INCENC_VALUE registers are held
B[8]: Enable: Enable for this incremental encoder
o
’0’ = Encoder is disabled
o
’1’ = Encoder is enabled
B[7:0]: Phase Filter: Selects if a particular state transition will cause the encoder counter to change.
For each bit:
o
’0’ = Transition will change counter
o
’1’ = Transition will not change counter.
The bit assignments for the transitions are:
Bit Previous State [B:A] Current State [B:A] Direction
7 00 10 Down
6 10 11 Down
5 11 01 Down
4 01 00 Down
3 10 00 Up
2 11 10 Up
1 01 11 Up
0 00 01 Up
6.2.15 FIFO_DATA_CNT (R
EAD
)
This register shows the current sample count that is available in the interval counter FIFO.
6.2.16 MAX_FIFO_SIZE (R
EAD
)
This register shows the max number of samples that the interval counter FIFO can hold.
6.2.17 THRESH_LOW (R
EAD
/W
RITE
)
Unsigned 32-bit value indicating the low threshold. If the count value goes below the threshold value, an interrupt will be generated. The
interrupt will only be generated once the threshold value is crossed.
6.2.18 THRESH_HIGH (R
EAD
/W
RITE
)
Unsigned 32-bit value indicating the high threshold. If the count value goes above the threshold value, an interrupt will be generated. The
interrupt will only be generated once the threshold value is crossed.
6.2.19 INCENC_VALUE (R
EAD
/W
RITE
)
The unsigned 32-bit current value of the incremental encoder channel. This is the same value that is written to the DMA FIFO.
This register does not update when MODE_CONFIG[HOLD] = 1.
This register can only be written to when MODE_CONFIG[Enable] = 0. This allows the counter to be pre-loaded with a known position value.
6.2.20 FIFO_ACCESS (R
EAD
)
This register provides direct access to the DMA FIFO. It can be used to access the data without the use of the DMA engine. The DMA engine
for this channel must be set to “Pause.” Each register access advances to the next sample.
If the MODE_CONFIG[HOLD] = 1, the last value before HOLD was enable will be written to the FIFO on each clock pulse, until HOLD is
disabled.