Ross Synergy 1, Руководство по обслуживанию

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Synergy 1 and Synergy 100 Maintenance Guide (v16-S1) System Architecture • 2–13
Aux Buses 3 to 10
Aux Buses 3 to 8 inclusive are untimed, and are switched directly on the crosspoint matrix. Refer to
the figure on on page 2–13.
Regarding timing, there is very little delay on the untimed Aux Bus outputs. The timed Aux Bus
outputs, however, are delayed such that they are timed to match the PGM output of the switcher.
Aux Buses 3 to 10 Routing
Phase Lock Loop and Sync Pulse Generator
The Phase Lock Loop ( PLL ) and Sync Pulse Generator ( SPG ) circuitry takes the reference video
signal from the REF IN BNC (in serial form) and creates a clean clock — plus various other sync
pulses for the system.
PLL and SPG Circuitry
Within the PLL and SPG circuitry, there are two modes in which the Deserializer Module
(4000A-061) can work:
• for reference
• as a 27 MHz clock
Both modes are discussed in the following sections.
24x8
Crosspoint
Matrix
Equalizers
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Cable
Driver
Aux 3 Out
Aux 4 Out
Aux 5 Out
Aux 6 Out
Aux 7 Out
Aux 8 Out
Aux 9 Out
Aux 10 Out
Reference
System Reference
and Clocking
Dedicated
Reference
Input
10-bit
SPG
H-Sync
V-Sync
Field Pulse
PLL
27MHz Clock
27MHz Clock
REF IN BNC