Rosch Computer EMB-M2, Руководство пользователя

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EMB-M2 User`s Manual 49
DRAM Timing Selectable
This item allows you to select the DRAM timing determined by the
timing information stored in SPD or set by the User manually. The
default is By SPD. When this field is set as By SPD, the DRAM
Timing items below will become read-only.
The choice: By SPD, Manual.
CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles
of CAS latency depends on the DRAM timing. Do not reset this field
from the default value specified by the system designer.
The choice: 3, 2.5, 2, 1.5.
Active to Precharge Delay
This item allows you to set the Active to Precharge Delay of DRAM
timing. Do not reset this field from the default value specified by the
system designer.
The choice: 6.
DRAM RAS# to CAS# Delay
When DRAM is refreshed, both rows and columns are addressed
separately. This field allows you to determine the timing of transition
from Row Address Strobe (RAS) to Column Address Strobe (CAS).
The choice: 3, 2.
DRAM RAS# Precharge
The precharge time is the number of cycles it takes for the RAS to
accumulate its charge before DRAM refresh. If insufficient time is
allowed, refresh may be incomplete and the DRAM may fail to retain
data.
The choice: 3, 2.