ROHS MC9S08QE128, Справочное руководство

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Internal Clock Source (S08ICSV3)
MC9S08QE128 MCU Series Reference Manual, Rev. 1.11
216 Freescale Semiconductor
11.4.7 External Reference Clock
The ICS module supports an external reference clock with frequencies between 31.25 kHz to 40 MHz in
all modes. When the ERCLKEN is set, the external reference clock signal will be presented as
ICSERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference
clock will not be used by the FLL and will only be used as ICSERCLK. In these modes, the frequency can
be equal to the maximum frequency the chip-level timing specifications will support (see the
Device
Overview chapter).
If EREFSTEN is set and the ERCLKEN bit is written to 1, the external reference clock will keep running
during stop mode in order to provide a fast recovery upon exiting stop.
11.4.8 Fixed Frequency Clock
The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source.
ICSFFCLK frequency must be no more than 1/4 of the ICSOUT frequency to be valid.
11.4.9 Local Clock
The ICS presents the low range DCO output clock divided by two as ICSLCLK for use as a clock source
for BDC communications. ICSLCLK is not available in FLL bypassed internal low power (FBILP) and
FLL bypassed external low power (FBELP) modes.