ML7404 Family LSIs
Hardware Design Manual
FEXL7404DG-03
7
3. PLL loop filter
Figure 3.1 shows a configuration example of the PLL loop filter circuit . C3 and R3 values depend on the data
rate to satisfy phase noise feature. The recommend values are listed in Table 3.1.
It is recommended to select the components with flat temperature characteristics and temperature coefficient is
managed. Capacitors, do not select high dielectric type and semiconductor type, so there is low accuracy and
non-linear temperature characteristics.
In order to prevent noise, the loop filter components (C3, R3 and C2) should be placed as close to the LP (#26)
pin as possible, recommends within 5 mm. Do not trace signal lines that become a noise source like a reference
clock line, around the loop filter.
Figure 3.1 PLL loop filter circuit configurations
Table 3.1 Representative component values for the loop filter
[Note] These component values appropriate for use on the LAPIS Semiconductor’s RF board. It is not
guaranteed to obtain same result on your specific board.
315~960MHz
C2
68pF
C3
1000pF
R3
6.2
kΩ
R101
N.M.
LP(#26)
C2
R3
C3
R101
