AN101
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11 July 2019
Page 13 of 27
3.5.2.
Wake-up and Back-to-Sleep
This example configures and enables the accelerometer to detect both wake-up and back-to-
sleep events using an external interrupt pin.
-
Write 0x00 to Control 1 (CNTL1) to set the accelerometer in stand-by mode
Register Name
Address
Value
CNTL1
0x1B
0x00
-
Write 0x06 to Output Data Control (ODCNTL) to set the Output Data Rate (ODR) of the
accelerometer to 50 Hz.
This step is optional as this is also a default setting.
Register Name
Address
Value
ODCNTL
0x21
0x06
-
Write 0x30 to Interrupt Control 1 (INC1) to enable physical interrupt pin INT1, set the polarity
of the physical interrupt to active high and configure for latched operation.
Register Name
Address
Value
INC1
0x22
0x30
-
Write 0x0A to Interrupt Control 4 (INC4) to set the Back to Sleep Interrupt (BTSI=1) and
Wakeup Interrupt (WUFI1) to be reported on physical interrupt pin INT1.
Register Name
Address
Value
INC4
0x25
0x0A
-
Write 0x3F to Interrupt Control 2 (INC2) to enable all positive and negative directions that can
cause a wakeup event.
Register Name
Address
Value
INC2
0x23
0x3F
-
Write 0xAE to Control 3 (CNTL3) to set output data rate for the wakeup engine (OWUF) to
50Hz.
Register Name
Address
Value
CNTL3
0x1D
0xAE
-
Write 0x76 to Control 4 (CNTL4) to set the counter mode to clear (C_MODE=0), threshold
mode to relative (TH_MODE=1), enable the wakeup function (WUFE=1), enable the back to
sleep function (BTSE=1), set pulse reject mode to standard operation and set the output data
rate for the back to sleep engine to 50Hz.
Register Name
Address
Value
CNTL4
0x1E
0x76
