± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr.
–
Ithaca, NY 14850
© 2019 Kionix
–
All Rights Reserved
tel: 607-257-1080 – fax:607-257-1146
894-12874-1907311402-0.17
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Page
34
of
73
TDTC
This register contains counter information for the detection of a double tap event. When the Directional-Tap
TM
ODR is
400Hz or less, every count is calculated as 1/ODR delay period. When the Directional-Tap
TM
ODR is 800Hz, every
count is calculated as 2/ODR delay period. When the Directional-Tap
TM
ODR is 1600Hz, every count is calculated as
4/ODR delay period. The Directional-Tap
TM
ODR is user-defined per Table 10. The TDTC counts starts at the beginning
of the fist tap and it represents the minimum time separation between the first tap and the second tap in a double tap
event. More specifically, the second tap event must end outside of the TDTC. The Kionix recommended default value
is 0.3 seconds (0x78).
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDTC7
TDTC6
TDTC5
TDTC4
TDTC3
TDTC2
TDTC1
TDTC0
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
01111000
Address:
0x2B
TTH
The Tap Threshold High (TTH) register represents the 8-bit jerk high threshold to determine if a tap is detected. The
value is compared against the upper 8 bits of the 16g output value (independent of the actual g-range setting of the
device). Though this is an 8-bit register, the register value is internally multiplied by two to set the high threshold. This
multiplication results in a range of 0 to 510 with a resolution of two counts. The Performance Index (PI) is the jerk signal
that is expected to be less than this threshold, but greater than the TTL threshold during single and double tap events.
Equation 1 shows how to calculate the Performance Index. The Kionix recommended default value is 51 (0x33). See
AN101 Getting Started
for recommended settings (
).
X’ = X (current) – X (previous)
Y’ = Y (current) – Y (previous)
Z’ = Z (current) – Z (previous)
PI = |X’| + |Y’| + |Z’|
Equation 1:
Performance Index
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TTH7
TTH6
TTH5
TTH4
TTH3
TTH2
TTH1
TTH0
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00110011
Address:
0x2C
TTL
The Tap Threshold Low (TTL) register represents the 8-bit (0-255) jerk low threshold to determine if a tap is detected.
The value is compared against the upper 8 bits of the 16g output value (independent of the actual g-range setting of
the device). The Performance Index (PI) is the jerk signal that is expected to be greater than this threshold and less
than the TTH threshold during single and double tap events. The Kionix recommended default value is 7 (0x07). See
AN101 Getting Started
for recommended settings (
).
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TTL7
TTL6
TTL5
TTL4
TTL3
TTL2
TTL1
TTL0
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00000111
Address:
0x2D