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© 2019 ROHM Co., Ltd.
No.64UG012E Rev.002
April.2021
User’s Guide
BD63xxxEFV-EVK-001
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0
500
1000
1500
2000
α[
V]
C
[pF]
Figure 5. C vs α
4.8 Clock input for advancing the electrical angle ( CLK Terminal )
T
rigger is CLK’s rising edge. The Electrical angle advances by one for each CLK input( 2.8 V < Hi < 5.0 V
、
0.6 V < Lo ).
This terminal is pull-
down to GND by 100 kΩ inside the IC.
4.9 Setting of smoothing capacitors in the power supply ( C1, C2 )
Please change the capacitance of the electrolytic capacitor (C1) of the power supply part, the ceramic capacitor (C2)
depending on the drive situation.
This evaluation board is connected with C1 = 100 µF, C2 = 0.1 µF.
5. Operation Explanation
5.1 Chopping Operation
The external capacitor(C0) and resistor(R0) connected to the CR Terminal is repeatedly charged and discharged between
the V
CRH
and V
CRL
levels. The output of the current detection comparator is masked while charging from V
CRL
to V
CRH
. As
mentioned above, this period defines the minimum ON-time. The CR Terminal begins discharging once the voltage reaches
V
CRH
. When the output current reaches the current limit during this period, then the IC enters decay mode. The CR continues
to discharge during this period until it reaches V
CRL
, at which point the IC output is switched back ON. The current output and
the CR Terminal begin charging simultaneously. The CR charge time (t
ONMIN
) and discharge time (t
DISCHARGE
) are set by
external components, according to the following formulas. The total of t
ONMIN
and t
DISCHARGE
yield the chopping period, t
CHOP
.
t
ONMIN
[s]
≒
C0
･
R'
･
R0 / (R'+R0)
･
ln[(VCR-0.4)/(VCR-1.0)]
VCR=V
･
R0/(R'+R0)
V : internal regulatorvoltage 5V(typ)
R': CR terminal internal impedance
5kΩ(typ)
t
DISCHARGE
[s]
≒
C0
･
R0
･
ln[(1+α)/0.4]
α:See the right graph.
t
CHOP
[s]
≒
t
ONMIN
+ t
DISCHARGE
