Rockwell Brooktree Bt848EVK, Техническое справочное руководство

Страница: 24 / 39

Bt848EVK Hardware Reference Guide
7
UG848_2A
Bt848
Electrical Description
Hardware Reference Guide
Brooktree
®
Bt848 Block
The Bt848 is a single-chip device for video capture over the PCI bus. In addition to video decoding
and scaling capability similar to those of the Bt829 video decoder, Bt848 provides an on-chip FIFO,
a DMA controller, PCI bus mastering capability, a general purpose I/O port, and I
2
C bus mastering
capability.
Power
The power systems for the Bt848 are described in the Power Block section.
Video Input
There are three sources of video information to the video decoder section of Bt848. The TV tuner is
connected to MUX0, Composite Video is connected to MUX1, and the S-Video input is connected
to the MUX2.
Video Output
The video data is output by the Bt848 DMA controller over the PCI bus.
Clock
The Bt848EVK accommodates NTSC or PAL/SECAM video formats. The Bt848 requires the
appropriate crystals and associated clock circuit as specified in the Bt848 datasheet.
I/O Block
I
2
C Bus
The TV tuner is controlled by Bt848 via the I
2
C bus. The clock and data pins are routed to the
appropriate pins on the tuner. Pull ups of 10 K
Ω
are provided to the +5 V plane. The protocol of the
bus and the possible commands may be found in the appropriate specifications for these devices.
GPIO Bus
The GPIO port is connected to two 40-pin connectors. The GPIO port can be used to input/output
general purpose data or video decoder data. Table 2 shows the mapping of the GPIO pins in both
general I/O and video decoder modes.