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RT8238A

14

www.richtek.com

RT8238A-07   January  2014

©

Copyright   2014 Richtek Technology Corporation. All rights reserved.                          is a registered trademark of Richtek Technology Corporation.

Layout Considerations

Layout is very important in high frequency switching
converter design. If the layout is designed improperly, the
PCB could radiate excessive noise and contribute to the
converter instability. The following points must be followed
for a proper layout of RT8238A.

`

Connect a filter capacitor to VCC, 1

μ

F to 4.7

μ

F range is

recommended. Place the filter capacitor close to the
IC.

`

Keep current limit setting network as close as possible
to the IC. Routing of the network should avoid coupling
to high voltage switching node.

`

Connections from the drivers to the respective gate of
the high side or the low side MOSFET should be as
short as possible to reduce stray inductance.

`

All sensitive analog traces and components such as
MODE, FB, GND, EN, PGOOD, CS, VCC, and TON
should be placed away from high voltage switching
nodes such as PHASE, LGATE, UGATE, or BOOT
nodes to avoid coupling. Use internal layer (s) as ground
plane (s) and shield the feedback trace from power traces
and components.

`

Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.

`

Power sections should connect directly to ground plane
(s) using multiple vias as required for current handling
(including the chip power ground connections). Power
components should be placed to minimize loops and
reduce losses.

Figure 5. Derating Curves for RT8238A Packages

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0

25

50

75

100

125

Ambient Temperature (°C)

Ma

xi

mu

m P

o

we

r Di

ss

ip

a

tio

n

 (

W

1

Single-Layer PCB

IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :

P

D(MAX)

 = (T

J(MAX)

 

 T

A

) / 

 θ

JA

where T

J(MAX)

 is the maximum operation junction

temperature 125

°

C, T

A

 is the ambient temperature and

the 

 θ

JA

 

is the junction to ambient thermal resistance.

For recommended operating conditions specification of
RT8238A, the maximum junction temperature is 125

°

C

and 

T

A

 is the ambient temperature. The junction to ambient

thermal resistance, 

θ

JA

, is layout dependent. For WQFN-

12L 2x2 packages, the thermal resistance, 

θ

JA

, is 165

°

C

/

W on a standard JEDEC 51-3 single-layer thermal test
board. The maximum power dissipation at 

T

A

 = 25

°

C

 can

be calculated by the following formula:

P

D(MAX)

 = (125

°

C

 

 25

°

C

) / (165

°

C

W) = 0.606W for

WQFN-12L 2x2 package

The maximum power dissipation depends on the operating
ambient temperature for fixed 

T

J(MAX)

 and thermal

resistance, 

θ

JA

. For the RT8238A package, the derating

curve in Figure 5 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.

Содержание RT8238A

Страница 1: ... excellent transient response and highDC output accuracy needed for stepping down high voltage batteries to generate low voltage CPU core I O and chipset RAM supplies in notebook computers The constant on time PWM control scheme handles wide input output voltage ratios with ease and provides 100ns instant on response to load transients while maintaining a relatively constant switching frequency Th...

Страница 2: ... the low side driver and the bootstrap circuit for high side driver Bypass to GND with a 1μF ceramic capacitor 6 FB VOUT Feedback Input Connect FB to a resistive voltage divider from VOUT to GND to adjust the output from 0 5V to 3 3V 7 MODE Pull down to GND for Forced CCM Mode Pull up to 2 5V for Audio Skipping Mode ASM Pull up to 5V for Diode Emulation Mode DEM 8 EN PWM Chip Enable Pull low to GN...

Страница 3: ...GATE PHASE PGOOD GND LGATE TON BOOT TRIG EN R Q S X 1 10 PWM MODE 90 VREF SS Timer POR CS VCC PHASE 10µA Pin No Pin Name Pin Function 9 PGOOD Open Drain Power Good Indicator High impedance indicates power is good 10 CS Current Limit Threshold Setting Input Connect a setting resistor to GND and the current limit threshold is equal to 1 10 of the voltage at this pin 11 TON On time Setting Connect a ...

Страница 4: ...85 C Absolute Maximum Ratings Note 1 z VCC FB PGOOD EN CS MODE to GND 0 3V to 6V z TONtoGND 0 3V to 32V z BOOT to PHASE 0 3V to 6V z PHASE to GND DC 0 3V to 32V 20ns 8V to 38V z UGATE to PHASE DC 0 3V to 6V 20ns 5V to 7 5V z LGATE toGND DC 0 3V to 6V 20ns 2 5V to 7 5V z Power Dissipation PD TA 25 C WQFN 12L 2x2 0 606W z Package Thermal Resistance Note 2 WQFN 12L 2x2 θJA 165 C W z Lead Temperature ...

Страница 5: ... FB 0 45V 250 400 550 ns Current Sensing Threshold CS Source Current VCS 0 5V to 2V 9 10 11 μA CS Source Current TC On the basis of 25 C 4700 ppm C Zero Crossing Threshold VMODE 1 8V Phase GND 10 5 mV ASM Min Frequency VMODE 2 5V 25 kHz Protection Function Current Limit Threshold GND PHASE VCS 1V 85 100 115 mV UVP Threshold UVP Detect FB Falling Edge 60 70 80 OVP Threshold OVP Detect FB Rising Edg...

Страница 6: ... Fault Propagation Delay Falling edge FB forced below PGOOD trip threshold 2 5 μs Output Low Voltage ISINK 1mA 0 4 V Leakage Current High state forced to 5V 1 μA Note 1 Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings Functional operation of the device at these or any other conditions beyond those indicated in the operational s...

Страница 7: ...ode CCMMode Efficiency vs Load Current 0 10 20 30 40 50 60 70 80 90 100 0 001 0 01 0 1 1 10 Load Current A Efficiency VIN 20V VOUT 1V DEMMode CCMMode Switching Frequency vs Load Current 0 50 100 150 200 250 300 350 400 0 001 0 01 0 1 1 10 Load Current A Switching Frequency kHz 1 VIN 12V VOUT 1V DEMMode CCMMode Switching Frequency vs Input Voltage 0 50 100 150 200 250 300 350 400 450 500 6 8 10 12 ...

Страница 8: ...CMMode OVP Time 200μs Div VOUT 500mV Div VIN 12V VOUT 1V No Load UGATE 20V Div LGATE 5V Div IL 10A Div Time 20μs Div UVP VIN 12V VOUT 1V No Load VOUT 500mV Div UGATE 50V Div LGATE 10V Div VOUT 500mV Div Power On from EN Time 1ms Div CCM Mode VIN 12V VOUT 1V No Load UGATE 20V Div EN 5V Div PGOOD 5V Div Power On from EN Time 1ms Div VOUT 500mV Div DEM Mode VIN 12V VOUT 1V No Load UGATE 20V Div EN 5V...

Страница 9: ...s reserved is a registered trademark of Richtek Technology Corporation Mode Transition CCM to DEM Time 1ms Div MODE 5V Div VIN 12V VOUT 1V No Load VOUT 200mV Div UGATE 20V Div LGATE 5V Div Mode Transition DEM to CCM Time 1ms Div MODE 5V Div VIN 12V VOUT 1V No Load VOUT 200mV Div UGATE 20V Div LGATE 5V Div ...

Страница 10: ...nternal on time capacitor The on time is the time required for the voltage on this capacitor to charge from zero volts to VOUT thereby making the on time of the high side switch directly proportional to the output voltage and inversely proportional to the input voltage The implementation results in a nearly constant switching frequency without the need of a clock generator Mode Selection Operation...

Страница 11: ... threshold Forced CCM Mode The low noise forced CCM mode MODE GND disables the zero crossing comparator which controls the low side switch on time This causes the low side gate drive waveform to become the complement of the high side gate drive waveform This in turn causes the inductor current to reverse at light loads as the PWM loop to maintain a duty ratio VOUT VIN The benefit of forced CCM mod...

Страница 12: ...t voltage PGOOD gets pulled low It is held low until the output voltage returns to within these tolerances once more In soft start PGOOD is actively held low and is allowed to transition high until soft start is over and the output reaches 93 of its set voltage There is a 2 5μs delay built into PGOOD circuitry to prevent false transitions POR UVLO and Soft Start Power On Reset POR occurs when VCC ...

Страница 13: ...t distinct ways including double pulsing and feedback loop instability to identify the unstable operation Double pulsing occurs due to noise on the output or because the ESR is too low that there is not enough voltage ramp in the output voltage signal This fools the error comparator into triggering a new cycle immediately after a 400ns minimum off time period has expired Double pulsing is more ann...

Страница 14: ...ower sections should connect directly to ground plane s using multiple vias as required for current handling including the chip power ground connections Power components should be placed to minimize loops and reduce losses Figure 5 Derating Curves for RT8238APackages 0 00 0 05 0 10 0 15 0 20 0 25 0 30 0 35 0 40 0 45 0 50 0 55 0 60 0 65 0 25 50 75 100 125 Ambient Temperature C Maximum Power Dissipa...

Страница 15: ... accurate and reliable However no responsibility is assumed by Richtek or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries Outline Dimension Symbol Dimensions In Millimeters Dimensions In Inches Min Max Mi...

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