*Notice: The information in this document is subject to change without notice
Tsi301
Notes
Tsi301 HyperTransport to PCI User Manual
3-20
bridge address range. However, these packets are also always forwarded.
•
Fence and Flush requests are never accepted by the HyperTransport PCI bridge and are always
forwarded.
•
Downstream response packets are accepted if their unitId field matches the value in the BaseUnitId
field of the HyperTransport PCI bridge LdtCmd register; otherwise, they are forwarded.
3.2.3 Collision Checking
Collision checking is performed according to the HyperTransport protocol to determine if incoming packets
are required to stay ordered behind packets already in the Rx buffers. Only packets headed to the same
accept or forward destination may have ordering requirements. If a packet has an ordering collision, it may not
be issued from the Rx buffers until the packet with which it collided has both been issued and reached an
appropriate commit point to guarantee ordering. This ordering point varies by destination.
Because the Outbound Request Controller (ORC) can reorder requests, requests accepted by the Hyper-
Transport PCI bridge may not be committed until they are retired by the ORC. For accesses to PCI, this
means that the request reached the PCI bus and all data was transferred. Packets forwarded from one link to
the other are streamed
- meaning that transmission may start before the whole packet is received. It is the
transmitter’s responsibility to ensure that required packet ordering is maintained so packets can be committed
as soon as they are passed to the other link controller.
Packets that do not have any ordering requirements may leave the Rx buffers in a different order than they
reached them, both between and within virtual channels. In general, the Rx buffers select a packet choosing
the oldest non-blocked packet in each channel to a given destination.
3.3 HyperTransport Address Map
HyperTransport implements a single flat 40-bit address space for all accesses. All address spaces that can
be reached from HyperTransport are mapped into this space. The HyperTransport PCI bridge checks
addresses on incoming packets in each space for subranges that it accepts.
3.3.1 Memory Mapped Space
The HyperTransport specification places Memory Mapped Space in the address range of 00_0000_0000h
to FC_FFFF_FFFFh. The HyperTransport PCI bridge accepts two ranges within this space, as enabled by
MemSpaceEn in the Command (Cmd) CSR, consisting of the following:
•
Memory Space, defined by the MemBase and MemLimit CSRs.
•
Prefetchable Memory Space, defined by the PrefMemBaseUpper/ PrefMemBase and
PrefMemLimitUpper/PrefMemLimit CSRs.
Setting the VgaEn bit in the BrCtrl CSR creates the additional window of 00_000A_0000h –
00_000B_FFFFh, which is also accepted. The HyperTransport PCI bridge never does prefetching to PCI, so
the prefetchable/nonprefetchable attribute of these ranges does not matter. RdSized requests to these ranges
result in MemRd requests on the PCI bus. WrSized requests to these ranges result in MemWr requests on the
PCI bus. If above 4 GB, addresses are passed straight through as a DAC.
3.3.2 I/O Space
The HyperTransport specification places PCI I/O space in the address range of FD_FC00_0000h to
FD_FDFF_FFFFh. The HyperTransport PCI bridge strips the top 15 bits off of addresses in this range.
•
If enabled by I/OSpaceEn in the Cmd CSR, the HyperTransport PCI bridge accepts requests that fall
in the range defined by the I/O Base and I/O Range Base Upper, and I/O Limit and I/O Range Limit
Upper CSRs.
•
If set, the IsaEn bit in the Bridge Control CSR creates a series of holes (the top 768 bytes of each 1 KB
block in the low 64 KB) in this space that the HyperTransport PCI bridge does not accept.
•
Setting the VgaEn bit in the Bridge Control CSR creates an additional set of windows (all addresses in
the low 64 KB where the bottom 10 bits are in the ranges 3B0h – 3BBh or 3C0h – 3DFh) which the
HyperTransport PCI bridge accepts. Accepted RdSized requests result in IoRd requests on the PCI
