Renesas S3A1, Руководство пользователя

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Target Board Kit S3A1 (TB-S3A1) Hardware Layout
R12UM0022EU0100 Rev.1.00 Page 14 of 36
Feb 6, 2018
Table 4 J-Link interface conflicts
Programming Interface Conflicting Interface
Port Use Interface Use
P108 SWDIO / JTAG TMS SPI SSLB0 fixed function, J1-13
P109 SWO / JTAG TDO SPI MOSIB fixed function, J1-7
P300 SWCLK / JTAG TCK GPT GTIOC0A fixed function, J1-31
4.4.3 JTAG/SWD
A 10-pin Cortex Debug Connector is provided at J10.
Table 5 JTAG / SWD connector (J10)
JTAG Connector TB-S3A1
Pin JTAG pin name SWD pin name Signal/Bus
1 VTref VTref +3V3
2 TMS SWDIO U1 P108/SWDIO (U1-51)
3 GND GND GND
4 TCK SWCLK U1 P300/SWCLK (U1-50)
5 GND GND GND
6 TDO SWO U1 P109 (U1-52)
7 Key Key N.C.
8 TDI NC/EXTb U1 P110 (U1-53)
9 GNDDetect GNDDetect
N.C. (short E31 to
connect to GND)
10 nSRST nSRST U1 RESET# (U1-38)
The Cortex
®
Debug Connector is fully described in the arm
®
CoreSight
™
Architecture Specification.
The J-Link MCU Power copper jumper and J-Link Disconnects copper jumpers may be open for proper operation of the
JTAG interface to prevent interactions with the J-Link MCU. See section 4.4.2 for details.
If a JTAG adapter is in use that properly interprets the arm
®
Cortex
®
10-pin Debug connector
assignment of pin 9 to GND, JTAG GNDDetect copper jumper E31 should be closed. If the JTAG
adapter used is one of several that may be confused or damaged by the presence of GND at pin 9, E31
should be open (as shipped).
The J-Link OB interface is multiplexed with the JTAG interface, and can collectively be referred to as the Programming
Interface. While the J-Link OB interface and the JTAG interface do not conflict, the J-Link OB signals may be isolated
from the programming interface by changing the copper jumpers as described in Section 4.4.2 Debug USB.
Four of the JTAG ports (P108, P109, P110 and P300) conflict with the SPI interface, as shown in the following table.