Renesas RL78/G1H, Руководство пользователя

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RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS
R01UH0575EJ0120 Rev. 1.20 Page 883 of 920
Dec 22, 2016
Note Use it with V
DD
≥ V
b
.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V
DD
tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V
IH
and
V
IL
, see the DC characteristics with TTL input buffer selected.
(Remarks are listed two pages after the next page.)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(T
A
= ‒ 40 to +85 ° C, 1.8 V
≤
V
DD
≤
3.6 V, V
SS
= 0 V) (1/3)
Parameter Symbol Conditions HS (high-speed main)
mode
LS (low-speed main)
mode
Unit
MIN. MAX. MIN. MAX.
SCKp cycle time t
KCY1
t
KCY1
≥ 4/f
CLK
2.7 V ≤ V
DD
< 3.6 V,
2.3 V
≤
Vb
≤
2.7 V,
Cb = 30 pF, Rb = 2.7 k Ω
500 1150 ns
1.8 V
≤
V
DD
< 3.3 V,
1.6 V
≤
Vb
≤
2.0 V
Note
,
Cb = 30 pF, Rb = 5.5 k Ω
1150 1150 ns
SCKp high-level width t
KH1
2.7 V
≤
V
DD
< 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 k Ω
t
KCY1
/2 ‒ 170 t
KCY1
/2 ‒ 170 ns
1.8 V ≤ V
DD
< 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note
,
Cb = 30 pF, Rb = 5.5 k Ω
t
KCY1
/2 ‒ 458 t
KCY1
/2 ‒ 458 ns
SCKp low-level width t
KL1
2.7 V ≤ V
DD
< 3.6 V,
2.3 V
≤
Vb
≤
2.7 V,
Cb = 30 pF, Rb = 2.7 k Ω
t
KCY1
/2 ‒ 18 t
KCY1
/2 ‒ 50 ns
1.8 V
≤
V
DD
< 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note ,
Cb = 30 pF, Rb = 5.5 k Ω
t
KCY1
/2 ‒ 50 t
KCY1
/2 ‒ 50 ns