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SH7211 Group

Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)

REJ06B0732-0100/Rev.1.00

March 2008

Page 12 of 13

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Description

Rev. Date

Page Summary

1.00

Mar.21.08

—

First edition issued

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Содержание REJ06B0732-0100

Страница 1: ...On chip RAM Areas with DMAC Cycle Stealing Mode Introduction This application note describes the operation of the DMAC and is intended for reference to help in the design of user software Target Devic...

Страница 2: ...st mode is used as the interrupt source for activating DMA transfer Cycle stealing mode is used as the bus mode 1 2 Used Module Direct memory access controller DMAC channel 0 1 3 Applicable Conditions...

Страница 3: ...DMA transfer in cycle stealing mode and burst mode are shown in figures 1 and 2 respectively In addition a block diagram of the DMAC is shown in figure 3 Table 1 Overview of DMAC Item Description Num...

Страница 4: ...atisfied The cycle stealing normal mode can be used in transfer across any interval regardless of the requesting source source and destination of the transfer Figure 1 DMA Transfer Example in Cycle St...

Страница 5: ...3 Peripheral bus Internal bus DMAC module Iteration control Register control Start up control Request priority control Bus interface Bus state controller Legend RDMATCR DMA reload transfer count regis...

Страница 6: ...est mode Channel CH0 Length of transfer data 4 bytes Maximum transfer count 128 transfers 128 data length of 4 bytes 512 byte data Address mode Dual address mode Bus mode Cycle stealing mode Priority...

Страница 7: ...typically handled by interrupts polling is used in this sample application A flowchart of the sample program is shown in figure 5 In addition a flowchart of DMAC initialization is shown in figure 6 Fo...

Страница 8: ...he count specified in DMATCR Set RLD to B 0 disable the reload function Set RS 3 0 resource selector to B 0100 auto request Set DM 1 0 to B 01 increment the destination address Set SM 1 0 to B 00 fix...

Страница 9: ...ster Name Address Setting Value Description Frequency control register FRQCR H FFFE0010 H 1303 CKOEN B 1 output clocks STC 1 0 B 00 frequency multiplication ratio of PLL circuit 1 IFC 2 0 B 000 intern...

Страница 10: ...TCR H FFFE1008 D 128 DMA transfer count 128 transfers H 0000 0000 Before DMA initialization DE B 0 disables DMA transfer H 8000 4410 DMA initialization TC B 1 transfers data for the count specified in...

Страница 11: ...8 Page 11 of 13 3 Documents for Reference Software Manual SH 2A SH2A FPU Software Manual The most up to date version of this document is available on the Renesas Technology Website Hardware Manual SH7...

Страница 12: ...2008 Page 12 of 13 Website and Support Renesas Technology Website http www renesas com Inquiries http www renesas com inquiry csc renesas com Revision Record Description Rev Date Page Summary 1 00 Ma...

Страница 13: ...e especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or underse...