P9235A-RB Layout Guide
© 2019 Integrated Device Technology, Inc
7
March 19, 2019
Routing of the FET gate driver lines away from switching nodes as much as possible (note 1). The traces are routed under the V
IN
and GND
planes (electrically quite areas). Also note the thick 30mil traces for the supply voltages (5V-note 2, 4; LDO33-note 5) and for the step down
switching regulator’s switch node (note 3). These thick traces prevent voltage drops when delivering the power, increasing reliability and
efficiency.
Figure 6. P9235A-RB Physical Layout from Demo PCB of Bottom Layer
GND Plane with Minimal Traces for Maximum Thermal Transfer
The outer layers of the PCB will be the most effective at transferring heat from the board to the ambient air or other objects. Spreading the
heat into internal layers is also effective for lowering the operating temperature. Internal layers can effectively spread heat horizontally when
they are not interrupted by traces and through-holes along their surface. An ideal layout will result in the entire PCB being close to the same
temperature; however, to obtain this result, ensure that all board layers have planes that are continuous and in direct contact with the
P9235A-RB thermal vias.
Select a single internal layer for routing most of the inner row/column pins to the rest of the PCB. The third layer is preferred for this purpose.
The required nodes for connecting heat spreading planes are GND, the V
IN
sources to the H bridge (V_BRIDGE, drain of Q2), and the switch
nodes (VLX1, VLX2). The other connections will spread heat due to natural thermodynamics, but the listed nodes contact the primary heat
sources of the P9235A-RB.
